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june 2016 docid028866 rev 1 1 / 173 this is information on a product in fu ll production. www.st.com bluenrg - 1 bluetooth ? low energy wireless system - on - chip datasheet - production data features ? bluetooth specification compliant m aster, slave and multiple roles simultaneously, single - mode bluetooth low energy system - on - chip ? operating supply voltage: from 1.7 to 3.6 v ? integrated linear regulator and dc - dc step - down converter ? operating temperature range: - 40 c to 105 c ? high perform ance, ultra - low power cortex - m0 32 - bit based architecture core ? programmable 160 kb flash ? 24 kb ram with retention (two 12 kb banks) ? 1 x uart interface ? 1 x spi interface ? 2 x i 2 c interface ? 14 or 15 gpio ? 2 x multifunction timer ? 10 - bit adc ? watchdog & rtc ? dm a controller ? pdm stream processor ? 16 or 32 mhz crystal oscillator ? 32 khz crystal oscillator ? 32 khz ring oscillator ? battery voltage monitor and temperature sensor ? up to +8 dbm available output power (at antenna connector) ? excellent rf link budget (up to 96 db) ? accurate rssi to allow power control ? 8.2 ma maximum tx current (@ 0 dbm, 3.0 v) ? down to 1 a current consumption with active ble stack (sleep mode) ? compliant with the following radio frequency regulations: etsi en 300 328, en 300 440, fcc cfr47 part 15 , arib std - t66 ? pre - programmed bootloader via uart ? qfn32, wcsp34 package option ? dedicated wettable flank qfn package for automotive grade qualification applications ? automotive product ? watches ? fitness, wellness and sports ? consumer medi cal ? security/proximity ? remote control ? home and industrial automation ? assisted living ? mobile phone peripherals ? lighting ? pc peripherals table 1: device summary table order code package packing bluenrg - 132 qfn32 (5 x 5 mm) tape and reel bluenrg - 134 wlcsp34 tape and reel bluenrg - 132y qfn32 (5 x 5 mm) automotive grade level tape and reel wlcsp34 qfn32
contents bluenrg - 1 2 / 173 docid028866 rev 1 contents 1 description ................................ ................................ ..................... 11 2 bluenrg - 1 bluetooth low energy stack ................................ ...... 12 3 functional details ................................ ................................ .......... 14 3.1 core ................................ ................................ ................................ 14 3.2 interrupts ................................ ................................ ......................... 14 3.3 memories ................................ ................................ ........................ 16 3.4 power management ................................ ................................ ........ 16 3.4.1 states description ................................ ................................ ............. 16 3.4.2 power saving strategy ................................ ................................ ...... 17 3.4.3 system controlle r registers ................................ ............................... 18 3.5 clocks and reset management ................................ ........................ 20 3.5.1 reset management ................................ ................................ .......... 21 3.5.2 reset and wakeup reason decoding ................................ ................ 22 3.5.3 switching to external clock ................................ ............................... 22 3.5.4 clock and reset registers ................................ ................................ .. 23 3.6 adc ................................ ................................ ................................ 27 3.6.1 introduction ................................ ................................ ....................... 27 3.6.2 functional overview ................................ ................................ .......... 27 3.6.3 adc registers ................................ ................................ ................... 30 3.7 dma ................................ ................................ ................................ 34 3.7.1 introduction ................................ ................................ ....................... 34 3.7.2 functional overview ................................ ................................ .......... 34 3.7.3 dma registers ................................ ................................ ................... 41 3.8 spi ................................ ................................ ................................ .. 49 3.8.1 introduction ................................ ................................ ....................... 49 3.8.2 functional overview ................................ ................................ .......... 50 3.8.3 spi registers ................................ ................................ ..................... 54 3.9 uart ................................ ................................ .............................. 61 3.9.1 introduction ................................ ................................ ....................... 61 3.9.2 functional description ................................ ................................ ....... 61 3.9.3 uart registers ................................ ................................ ................. 69 3.10 i2c ................................ ................................ ................................ .. 82 3.10.1 introduction ................................ ................................ ....................... 82 3.10.2 functional description ................................ ................................ ....... 82 3.10.3 i 2 c registers ................................ ................................ ...................... 84
bluenrg - 1 contents docid028866 rev 1 3 / 173 3.11 flash co ntroller ................................ ................................ .............. 101 3.11.1 flash controller introduction ................................ ........................... 101 3.11.2 flash controller functional description ................................ ............ 101 3.11.3 flash controller registers ................................ ................................ 104 3.12 gpio ................................ ................................ ............................. 108 3.12.1 introduction ................................ ................................ ..................... 108 3.12.2 functional description ................................ ................................ ..... 108 3.12.3 gpio registers ................................ ................................ ................ 111 3.13 mft ................................ ................................ ............................... 116 3.13.1 mft introduction ................................ ................................ ............. 116 3.13.2 mft functional description ................................ ............................. 116 3.13.3 mft registers ................................ ................................ ................. 126 3.14 watchdog ................................ ................................ ...................... 128 3.14.1 introduction ................................ ................................ ..................... 128 3.14.2 functional description ................................ ................................ ..... 129 3.14.3 watchdog registers ................................ ................................ ......... 129 3.15 rtc ................................ ................................ ............................... 132 3.15.1 introduction ................................ ................................ ..................... 132 3.15.2 functional description ................................ ................................ ..... 132 3.15.3 rtc registers ................................ ................................ ................. 134 3.16 rng ................................ ................................ .............................. 141 3.16.1 introduction ................................ ................................ ..................... 141 3.16.2 functional description ................................ ................................ ..... 141 3.16.3 rng registers ................................ ................................ ................. 141 3.17 pdm stream processor ................................ ................................ . 142 3.18 system timer (systick) ................................ ................................ . 142 3.19 tx/rx event alert ................................ ................................ .......... 142 3.20 swd debug feature ................................ ................................ ....... 143 3.20.1 de bugging tips ................................ ................................ ................ 143 3.21 bluetooth low energy radio ................................ ............................ 143 3.21.1 radio operating modes ................................ ................................ .. 143 3.22 pre - programmed bootloader ................................ ......................... 144 4 pin description ................................ ................................ ............ 145 5 memory mapping ................................ ................................ ......... 149 6 application circuit ................................ ................................ ....... 151 7 absolute maximum ratings and thermal data ........................... 154
contents bluenrg - 1 4 / 173 docid028866 rev 1 8 general characte ristics ................................ ............................... 155 9 electrical specification ................................ ................................ 156 9.1 electrical characteristics ................................ ................................ 156 9.1.1 peripheral current consumption ................................ ..................... 157 9.2 rf general characteristics ................................ ............................ 157 9.3 rf transmitter characteristics ................................ ........................ 158 9.4 rf receiver characteristics ................................ ............................ 158 9.5 high speed crystal oscillator characteristics ................................ .. 160 9.5.1 high speed crystal oscillator ................................ ........................... 161 9.6 low speed crystal oscillator characteristics ................................ .. 162 9.7 high speed ring oscillator characteristics ................................ ...... 162 9.8 low speed ring oscillator characteristics ................................ ....... 162 9.9 n - fractional frequency synthesi zer characteristics ........................ 162 9.10 auxiliary blocks characteristics ................................ ...................... 163 10 package information ................................ ................................ ... 165 10.1 qfn32 package information ................................ ......................... 166 10.2 wlcsp34 package information ................................ .................... 168 11 pcb assembly guidelines ................................ ........................... 170 12 revision history ................................ ................................ .......... 172
bluenrg - 1 list of tables docid028866 rev 1 5 / 173 list of tables table 1: device summary table ................................ ................................ ................................ .................. 1 table 2: interrupt vectors ................................ ................................ ................................ .......................... 15 table 3: relationship between bluenrg - 1 states and functional blocks ................................ ................ 17 table 4: system_ctrl registers ................................ ................................ ................................ ........... 18 table 5: system_ctrl - wkp_io_is register description: address offset system_ctrl_base_addr+0x00 ................................ ................................ ................................ ...... 18 table 6: system_ctrl - wkp_io_ie register description: address offset system_ctrl_base_addr+0x04 ................................ ................................ ................................ ...... 19 table 7: system_ctrl - ctrl register description: address offs et system_ctrl_base_addr+0x08 ................................ ................................ ................................ ...... 19 table 8: ahbupconv registers ................................ ................................ ................................ .............. 19 table 9: blue_ctrl registers ................................ ................................ ................................ ................ 19 table 10: ckgen_soc registers ................................ ................................ ................................ ............ 23 table 11: ckgen_soc - control register description: address offset ckgen_soc_base_addr+0x00 ................................ ................................ ................................ ......... 23 table 12: ckgen_soc - reason_rst register description: address offset ckgen_soc_base_addr+0x08 ................................ ................................ ................................ ......... 24 table 13: ckgen_soc - die_id register description: address of fset ckgen_soc_base_addr+0x1c ................................ ................................ ................................ ......... 24 table 14: ckgen_soc - clock_en register description: address offset ckgen_soc_base_addr+0x20 ................................ ................................ ................................ ......... 24 table 15: ckgen_soc - dma_config register description: address offset ckgen_soc_base_addr+0x24 ................................ ................................ ................................ ......... 25 table 16: ckgen_ble registers ................................ ................................ ................................ ............. 25 table 17: ckgen_ble - reason_rst register description: address offset ckgen_ble_base_addr+0x08 ................................ ................................ ................................ .......... 25 table 18: ckgen_ble - clk32k_count register description: address offset ckgen_ble_base_add r+0x0c ................................ ................................ ................................ .......... 26 table 19: ckgen_ble - clk32k_period register description: address offset ckgen_ble_base_addr+0x10 ................................ ................................ ................................ .......... 26 table 20: ckgen_b le - clk32k_freq register description: address offset ckgen_ble_base_addr+0x14 ................................ ................................ ................................ .......... 26 table 21: ckgen_ble - clk32k_it register description: address offset ckgen_ble_base_addr+0x18 ................................ ................................ ................................ .......... 26 table 22: adc channels ................................ ................................ ................................ ........................... 27 table 23: adc data rate ................................ ................................ ................................ ........................... 28 table 24: adc data rate with microphone mode ................................ ................................ ...................... 28 table 25: adc registers ................................ ................................ ................................ ............................ 30 table 26: adc - ctrl register description: address offset adc_base_addr+0x00 ........................... 30 table 27: adc - conf register description: address offset adc_base_addr+0x04 .......................... 31 table 28: adc - irqstat register description: address offset adc_base_addr+0x08 ..................... 32 table 29: adc - irqmask register description: address offset adc_base_addr+0x0c ................... 33 table 3 0: adc - data_conv register description: address offset adc_base_addr+0x14 .............. 33 table 31: adc - offset register description: address offset adc_base_addr+0x18 ...................... 33 table 32: adc - sr_reg register description: address offset adc_base_addr+0x20 ..................... 33 table 33: adc - threshold_hi register description: address offset adc_base_add r+0x24 ........ 34 table 34: adc - threshold_lo register description: address offset adc_base_addr+0x28 ....... 34 table 35: programmable data wi dth and endian behavior (when bits pinc = minc = 1) ....................... 37 table 36: dma interrupt requests ................................ ................................ ................................ ............. 40 table 37: dma registers ................................ ................................ ................................ ........................... 41 table 38: dma - isr register description: address offset dma_base_addr+0x00 ............................. 41 table 39: dma - ifcr register description: address offset d ma_base_addr+0x04 ........................... 45 table 40: dma_chx registers ................................ ................................ ................................ .................. 47
list of tables bluenrg - 1 6 / 173 docid028866 rev 1 table 41: dma_chx - ccr register description: address offset dma_chx_base_ad dr+0x00 ......... 48 table 42: dma_chx - cndtr register description: address offset dma_chx_base_addr+0x04 .... 49 table 43: dma_chx - cpar reg ister description: address offset dma_chx_base_addr+0x08 ....... 49 table 44: dma_chx - cmar register description: address offset dma_chx_base_addr+0x0c ..... 49 table 45: spi clock phase and clock polarity ................................ ................................ ........................... 50 table 46: spi tx endianness ................................ ................................ ................................ ................... 51 table 47: spi rx endianness ................................ ................................ ................................ ................... 51 table 48: spi registers ................................ ................................ ................................ ............................. 54 table 49: spi - cr0 register description: address offset spi_base_addr+0x00 ................................ . 54 table 50: spi - cr1 register description: address offset spi_base_addr+0x04 ................................ . 55 table 51: spi - dr register description: address offset spi_base_addr +0x08 ................................ ... 57 table 52: spi - sr register description: address offset spi_base_addr+0x0c ................................ .. 57 table 53: spi - cpsr register description : address offset spi_base_addr+0x10 .............................. 57 table 54: spi - imsc register description. address offset spi_base_addr+0x14. ............................. 58 table 55 : spi - ris register description: address offset spi_base_addr+0x18 ................................ .. 58 table 56: spi - mis register description: address offset spi_base_addr+0x1c ................................ . 58 table 57: spi - icr register description: address offset spi_base_addr+0x20 ................................ .. 59 table 58: spi - dmacr register description: address offset spi_base_addr+0x24 ........................... 59 table 59: spi C rxfrm register description: address offset spi_base_addr+0x28 .......................... 59 table 60: spi C chn register description: address offset spi_base_addr+0x2c ............................... 59 table 61: spi C wdtxf register description: address offset spi_base_addr + 0x30 ........................ 60 table 62: spi - itcr re gister description: address offset spi_base_addr+0x80 ............................... 60 table 63: spi C tdr register description: address offset spi_base_addr+0x8c ............................... 60 table 64: rx fifo errors ................................ ................................ ................................ ......................... 61 table 65: typical baud rates with ovsfact = 0 ................................ ................................ ..................... 63 table 66: typical baud rates with ovsfact = 1 ................................ ................................ ..................... 64 table 67: control bits to enable and disable hardware flow control ................................ ......................... 65 table 68: control bits to enable and program receive software flow control ................................ ............ 65 table 69: control bits to enable and program transmit software flow control ................................ .......... 6 6 table 70: uart register s ................................ ................................ ................................ ......................... 69 table 71: uart - dr register description: address offset uart_base_addr+0x00 ........................... 70 table 72: uart - rsr register description: address offset uart_base_addr+0x04 ........................ 70 table 73: uart - timeout register description: address offset uart_base_addr+0x0c ............... 71 table 74: uart - fr register description: address offset uart_base_addr+0x18 ........................... 71 table 75: uart - lcrh_rx register description: address offset uart_base_addr+0x1c .............. 72 table 76: uart - ibrd register description: address offset uart_base_addr+0x24 ....................... 73 table 77: uart - fbrd register description: address offset uart_base_addr+0x28 ...................... 73 table 78: uart - lcrh_tx register description: address offset uart_base_addr+0x2c ............... 74 table 79: uart - cr register descriptio n: address offset uart_base_addr+0x30 ........................... 75 table 80: uart - ifls register description: address offset uart_base_addr+0x34 ........................ 76 table 81: uart - imsc register description: address offset uart_base_addr+0x38 ....................... 76 table 82: uart - ris register description: address offset uart_base_addr+0x3c ......................... 77 table 83: uart - mis register description: address offset uart_base_addr+0x40 ......................... 78 table 84: uart - icr register description: address offset uart_base_addr+0x44 .......................... 79 table 85: uart - dmacr register description: address offset uart_base_addr+0x48 .................. 80 table 86: uart - xfcr register description: a ddress offset uart_base_addr+0x50 ...................... 80 table 87: uart - xon1 register description: address offset uart_base_addr+0x54 ...................... 81 table 88: uart - xon2 register description. address offset uart_base_addr+0x58. .................... 81 table 89: uart - xoff1 register description. address offset uart_base_addr+0x5c. .................. 81 table 90: uart - xoff2 register description. address offset uart_base_addr+0x60. ................... 81 table 91: i2cx registers ................................ ................................ ................................ ............................ 84 table 92: i2c - cr register description: address offset i2cx_base_addr+0x00 ................................ . 85 table 93: i2c - scr register description: address offset i2cx_base_addr+0x04 .............................. 87 table 94: i2c2 - mcr register description: address offset i2cx_base_addr+0x0c ........................... 87 table 95: i2c - tfr register description: address offset i2cx_base _addr+0x10 ............................... 89
bluenrg - 1 list of tables docid028866 rev 1 7 / 173 table 96: i2c - sr register description: address offset i2cx_base_addr+0x14 ................................ . 89 table 97: i2c - rfr register descri ption: address offset i2cx_base_addr+0x18 .............................. 91 table 98: i2c - tftr register description: address offset i2cx_base_addr+0x1c ............................ 91 ta ble 99: i2c - rftr register description: address offset i2cx_base_addr+0x20 ............................ 91 table 100: i2c - dmar register description: address offset i2cx_base_addr+0x24 ......................... 91 table 101: i2c - brcr register description: address offset i2cx_base_addr+0x28 .......................... 92 table 102: i2c - imscr register description: address offset i2cx_base_addr+0x 2c ....................... 92 table 103: i2c - risr register description: address offset i2cx_base_addr+0x30. .......................... 94 table 104: i2c - misr register descript ion: address offset i2cx_base_addr+0x34 ........................... 97 table 105: i2c - icr register description: address offset i2cx_base_addr+0x38 .............................. 99 tabl e 106: i2c - thddat register description: address offset i2cx_base_addr+0x4c .................. 100 table 107: i2c - thdsta_fst_std register description: address offset i2cx_base_addr+0x50 . 100 table 108: i2c - tsusta_fst_std register description: address offset i2cx_base_addr+0x58 . 100 table 109: flash commands ................................ ................................ ................................ .................. 104 table 110: flash interface timing ................................ ................................ ................................ ............ 104 table 111: flash controller registers ................................ ................................ ................................ .... 104 table 1 12: flash C command register description: address offset flash_base_addr+0x00 .... 105 table 113: flash C config register description: address offset flash_base_addr+0x04 ......... 105 table 114: flash - irqstat register description: address offset flash_base_addr+0x08 ........ 105 table 115: flash - irqmask register description: address offs et flash_base_addr+0x0c ....... 106 table 116: flash - irqraw register description: address offset flash_base_addr+0x10 ......... 106 table 117: f lash C size register description: address offset flash_base_addr+0x14 ............... 106 table 118: flash C address register description: address offset flash_base_addr+0x18 ...... 106 table 119: flash C lfsrval register description: address offset flash_base_addr+0x24 ....... 106 table 120: flash C timetrim1 register description: address offset fl ash_base_addr+0x28 .... 106 table 121: flash C timetrim2 register description: address offset flash_base_addr+0x2c ... 107 table 122: fla sh C timetrim3 register description: address offset flash_base_addr+0x30 .... 107 table 123: flash C data0 register description: address offset flash_base_addr+0x40 ............ 107 table 124: flash C data1 register description: address offset flash_base_addr+0x44 ............ 107 table 125: flash C data2 register description: address offset flash_b ase_addr+0x48 ............ 107 table 126: flash C data3 register description: address offset flash_base_addr+0x4c ........... 107 table 127: io functiona l map ................................ ................................ ................................ .................. 108 table 128: gpio interrupt modes ................................ ................................ ................................ ........... 109 table 129: pin characteristics ................................ ................................ ................................ ................. 109 table 130: io pull values ................................ ................................ ................................ ........................ 109 table 131: gpio registers ................................ ................................ ................................ ...................... 111 table 132: gpio C data register description: addres s offset gpio_base_addr+0x00 ................... 112 table 133: gpio C oen register description: address offset gpio_base_addr+0x04 ..................... 112 table 134: g pio C pe register description: address offset gpio_base_addr+0x08 ........................ 112 table 135: gpio C ds register description: address offset gpio_base_addr+0x0c ....................... 112 table 136: gpio C is register description: address offset gpio_base_addr+0x10 ......................... 113 table 137: gpio C ibe register description: address offset gpio_base_addr+0x14 ....................... 113 table 138: gpio C iev register description: address offset gpio_base_addr+0x18 ....................... 113 table 139: gpio C ie register description: addre ss offset gpio_base_addr+0x1c ......................... 113 table 140: gpio C mis register description: address offset gpio_base_addr+0x24 ...................... 113 table 141: gpio C ic register description: address offset gpio_base_addr+0x28 ......................... 113 table 142: gpio - mode0 register description: address offset gpio_base_addr+0x2c ................ 113 table 143: gpio C mode1 register description: address offset gpio_base_addr+0x30 ................ 114 table 144: gpio C dats register description: address offset gpio_base_addr+0x3c .................. 114 table 145: gpio C datc register description: address offset gpio_base_addr+0x40 ................... 115 table 146: gpio - mftx register descrip tion: address offset gpio_base_addr+0x44 .................... 115 table 147: mft modes ................................ ................................ ................................ ........................... 116 table 148: mft io functions ................................ ................................ ................................ .................. 124 table 149: mft interrupt functions ................................ ................................ ................................ ......... 125 table 150: mftx registers ................................ ................................ ................................ ..................... 126 table 151: mftx C tnc nt1 register description: address offset mftx_base_addr+0x00 ............. 126
list of tables bluenrg - 1 8 / 173 docid028866 rev 1 table 152: mftx C tncra register description: address offset mftx_base_addr+0x04 .............. 126 table 153: mftx C tncrb register description: address offset mftx_base_addr+0x08 .............. 126 table 154: mftx C tncnt2 register description: address offset mftx_base_addr+0x0c ............ 126 table 155: mftx C tnprsc register description: address offset mftx_base_addr+0x10 ............ 126 table 156: mftx - tnckc register descript ion: address offset mftx_base_addr+0x14 ............... 127 table 157: mftx - tnmctrl register description: address offset mftx_base_addr+0x18 .......... 127 table 158: mftx - tnictrl register description: address offset mftx_base_addr+0x1c ............ 128 table 159: mftx - tniclr register description: address offset mftx_base_addr+0x20 ............... 128 table 160: watchdog interrupt interval ................................ ................................ ................................ ... 129 table 161: wdg registers ................................ ................................ ................................ ...................... 129 table 16 2: wdg - lr register description: address offset wdg_base_addr+0x00 ......................... 130 table 163: wdg - val register description: address offset wdg_base_addr+0x04 ....................... 130 table 164: wdg - cr register description: address offset wdg_base_addr+0x08 ......................... 130 table 165: wdg - icr register description: address offset wdg_base_addr+0x0c ....................... 130 table 166: wdg - ris register description: address offset wdg_base_addr+0x10 ........................ 131 table 167: wdg - mis register description: address of fset wdg_base_addr+0x14 ....................... 131 table 168: wdg - lock register description: address offset wdg_base_addr+0xc00 ................. 131 table 169: rtc mo des ................................ ................................ ................................ ........................... 132 table 170: rtc registers ................................ ................................ ................................ ........................ 134 table 171: rtc - cwdr register description: address offset rtc_base_addr+0x00 ..................... 135 table 172: rtc - cwdmr register description: address offset rtc_base_addr+0x04 .................. 136 table 173: rtc - cwdlr register description: address o ffset rtc_base_addr+0x08 ................... 136 table 174: rtc - cwyr register description: address offset rtc_base_addr+0x0c ..................... 137 table 175: rtc - cwymr register description: address offset rtc_base_addr+0x10 ................... 137 table 176: rtc - cwylr register description: address offset rtc_base_addr+0x14 .................... 137 table 177: rtc - ctcr register description: address offset rtc_base_addr+0x18 ....................... 138 table 178: rtc - imsc register description: address offset rtc_base_addr+0x1c ....................... 138 table 179: rtc - ris register description: address offset rtc_base_addr+0x20 ........................... 139 table 180: rtc - mis register description: address off set rtc_base_addr+0x24. ......................... 139 table 181: rtc - icr register description: address offset rtc_base_addr+0x28 .......................... 139 table 182: rtc C td r register description: address offset rtc_base_addr+0x2c ........................ 139 table 183: rtc - tcr register description: address offset rtc_base_addr+0x30 ......................... 139 table 184: rtc C tlr1 register description: address offset rtc_base_addr+0x34 ....................... 140 table 185: rtc C tlr2 register description: address offset rtc_base_addr+0x38 ....................... 140 table 186: rtc C tpr1 register description: address offset rtc_base_addr+0x3c ...................... 140 table 187: rtc C tpr2 register description: address offset rtc_base_addr+0x40 ....................... 140 table 188: rtc C tpr3 register description: address offset rtc_base_addr+0x44 ....................... 140 table 189: rtc C tpr4 r egister description: address offset rtc_base_addr+0x48 ....................... 141 table 190: rtc C tin register description: address offset rtc_base_addr+0x4c ......................... 141 table 191: rng registers ................................ ................................ ................................ ....................... 141 table 192: rng C cr register description: address offset rng_base_addr+0x00 ......................... 141 table 1 93: rng C sr register description: address offset rng_base_addr+0x04 .......................... 142 table 194: rng C val register description: address offset rng_base_addr+0x08 ........................ 142 table 195: swd port ................................ ................................ ................................ .............................. 143 table 196: pinout description ................................ ................................ ................................ ................. 147 table 197: memory mapping ................................ ................................ ................................ .................. 149 table 198: external component list ................................ ................................ ................................ ........ 153 table 199: absolute maximum ratings ................................ ................................ ................................ ... 154 table 200: thermal data ................................ ................................ ................................ ......................... 154 table 201: recommended operating conditions ................................ ................................ .................... 155 table 202: electrical characteristics ................................ ................................ ................................ ....... 156 table 203: peripheral current consumption ................................ ................................ ............................ 157 table 204: rf general characteristics ................................ ................................ ................................ .... 157 table 205: rf transmitter characteristics ................................ ................................ .............................. 158 table 206: rf receiver characteristics ................................ ................................ ................................ ... 158
bluenrg - 1 list of tables docid028866 rev 1 9 / 173 table 207: high speed cr ystal oscillator characteristics ................................ ................................ ......... 160 table 208: low speed crystal oscillator characteristics ................................ ................................ .......... 162 table 209: high speed ring osci llator characteristics ................................ ................................ ............. 162 table 210: low speed ring oscillator characteristics ................................ ................................ .............. 162 table 211: n - fractional frequency synthesize r characteristics ................................ .............................. 163 table 212: auxiliary blocks characteristics ................................ ................................ ............................. 163 table 213: qfn32 (5 x 5 x 1 pitch 0.5 mm) mechanical data ................................ ................................ 167 table 214: wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data ................................ .............. 169 table 215: flip chip csp (2.71 x 2.58 x 0.5 pitch 0. 4 mm) package reflow profile recommendation ... 170
list of figures bluenrg - 1 10 / 173 docid028866 rev 1 list of figures figure 1: bluenrg - 1 architecture block diagram ................................ ................................ ..................... 11 figure 2: bluenrg - 1 single chip rf software layers ................................ ................................ ............... 12 figure 3: bluenrg - 1 network processor rf software layers ................................ ................................ ... 13 figure 4: bluenrg - 1 power management state machine ................................ ................................ ........ 16 figure 5: clock tree ................................ ................................ ................................ ................................ ... 20 figure 6: reset and wakeup generation ................................ ................................ ................................ ... 21 figure 7: block diagram of adc ................................ ................................ ................................ ............... 27 figure 8: dma request mapping in bluenrg - 1 ................................ ................................ ....................... 41 figure 9: uart character frame ................................ ................................ ................................ ............... 62 figure 10: hardware flow control between two similar devices ................................ ................................ 64 figure 11: pwm signal ................................ ................................ ................................ ............................ 117 figure 12: mft mode 1 block diagram ................................ ................................ ................................ ... 118 figure 13: mft mode 1a block diagram ................................ ................................ ................................ . 119 figure 14: mft mode 2 block diagram ................................ ................................ ................................ ... 121 figure 15: mft mode 3 block diagram ................................ ................................ ................................ ... 122 figure 16: mft mode 4 bloc k diagram ................................ ................................ ................................ ... 123 figure 17: bluenrg - 1 pin out top view (qfn32) ................................ ................................ ................... 145 figure 18: bluenrg - 1 ball out top view (wcsp34) ................................ ................................ ............... 146 figure 19: bluenrg - 1 ball out bottom view (wcsp34) ................................ ................................ ......... 147 figure 20: application circuit: active dc - dc converter qfn32 package ................................ ............... 151 figure 21: application circuit: non - active dc - dc converter qfn32 package ................................ ........ 151 figure 22: application circuit: active dc - dc converter wcsp34 p ackage ................................ ............ 152 figure 23: application circuit: non active dc - dc converter wcsp34 package ................................ ..... 152 figure 24: high speed oscillator block diagram ................................ ................................ ...................... 161 figure 25: qfn32 (5 x 5 x 1 pitch 0.5 mm) package outline ................................ ................................ .. 166 figure 26: qfn32 (5 x 5 x 1 pitch 0.5 mm) package det ail "a" ................................ ............................. 167 figure 27: wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline ................................ ................ 168 figure 28: flip chip csp (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation .... 170
bluenrg - 1 description docid028866 rev 1 11 / 173 1 description the bluenrg - 1 is a very low power bluetooth low energy (ble) single - mode system - on - chip, compliant with bluetooth specification. th e bluenrg - 1 extends the features of award - winning bluenrg network processor, enabling the usage of the embedded cortex m0 for running the user application code. the bluenrg - 1 includes 160 kb of programming flash memory, 24 kb of static ram memory with rete ntion (two 12 kb banks) and spi, uart, i 2 c standard communication interface peripherals. it also features multifunction timers, watchdog, rtc and dma controller. an adc is available for interfacing with analog sensors, and for reading the measurement of th e integrated battery monitor. a digital filter is available for processing a pdm stream. the bluenrg - 1 offers the same excellent rf performance of the bluenrg radio, and the integrated high efficiency dc/dc converter keeps the same ultra - low power charact eristics, but the bluenrg - 1 improves the bluenrg sleep mode current consumption allowing a further increase in the battery lifetime of the applications. figure 1 : bluenrg - 1 architecture block diagram
bluenrg - 1 bluetooth low energy stack bluenrg - 1 12 / 173 docid028866 rev 1 2 bluenrg - 1 bluetooth low energ y stack the bluenrg - 1 is complemented with a bluetooth low energy stack c library that provides: ? master, slave role support ? gap: central, peripheral, observer or broadcaster roles ? att/gatt: client and server ? sm: privacy, authenticat ion and authorization. ? l2cap ? link layer: aes - 128 encryption and decryption the bluenrg - 1 can be configured for supporting single chip or network processor applications. in the first configuration, the bluenrg - 1 operates as single device in the application for managing both the application code and the bluetooth low energy stack. the whole bluetooth low energy stack is provided as object code in a single library file whereas the gatt low energy profiles are provided as object codes in separate libraries. figure 2: "bluenrg - 1 single chip rf software layers" shows the single chip rf software layers. figure 2 : bluenrg - 1 single chip rf software layers the bluenrg - 1 can be configured for operating as a network coprocessor. in this case a dedicated firmware is provided for supporting the interface with an external application
bluenrg - 1 blu enrg - 1 bluetooth low energy stack docid028866 rev 1 13 / 173 processor. the whole bluetooth low energy stack runs in the bluenrg - 1; the gatt profiles are provided for running in the applicatio n processor together with the application code. figure 2: "bluenrg - 1 single chip rf software layers" shows the network processor rf software layers. figure 3 : bluenrg - 1 network processor rf software layers
functional details bluenrg - 1 14 / 173 docid028866 rev 1 3 functional details the bluenrg - 1 integrates the blocks listed below: ? cortex m0 core ? interrupts management ? 160 kb flash memory ? 24 kb of ram with two retention options (12 kb or 24 kb) ? power management ? clocks ? bluetooth low ene rgy radio ? random number generator (rng) (it is reserved to bluetooth low energy protocol stack, but user application can read it) ? public key cryptography (pka) (reserved to bluetooth low energy protocol stack) ? peripherals: ? spi interface ? uart interface ? i 2 c bus interface ? gpio ? multifunction timer ? dma controller ? watchdog ? rtc ? adc with battery indicator ? pdm stream processor the main blocks are described in the following subsection. 3.1 core the arm ? cortex ? - m0 processor has been developed to pro vide a low - cost platform that meets the needs of mcu implementation, with a reduced pin count and low - power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm ? cortex ? - m0 32 - bit risc p rocessor features exceptional code - efficiency, delivering the high - performance expected from an arm core in the memory size usually associated with 8 - bit and 16 - bit devices. the bluenrg - 1 has an embedded arm core and is therefore compatible with all arm to ols and software. 3.2 interrupts the cortex - m0 nested vector interrupt controller (nvic) handles interrupts. the nvic controls specific cortex - m0 interrupts (address 0x00 to 0x3c) as well as 32 - user interrupts (address 0x40 to 0xbc). in t he bluenrg - 1 device, the user interrupts are connected to the interrupt signals of the different peripherals.
bluenrg - 1 functional details docid028866 rev 1 15 / 173 table 2: interrupt vectors position priority priority type description address initial main sp 0x0000_0000 - 3 fixed reset handler 0x0000_000 4 - 2 fixed nmi handler 0x0000_0008 - 1 fixed hardfault handler 0x0000_000c reserved 0x0000_000c C 0x0000_0028 3 settable svc handler 0x0000_002c reserved 0x0000_0030 - 0x0000_0034 5 settable pendsv handler 0x0000_0038 6 settable systemtick handler 0x0000_003c 0 init 0 settable gpio interrupt 0x0000_0040 1 init 0 settable flash controller interrupt 0x0000_0044 2 init 0 settable reserved 0x0000_0048 3 init 0 settable reserved 0x0000_004c 4 init 0 settable uart interrupt 0x0000_0050 5 in it 0 settable spi interrupt 0x0000_0054 6 init 0 critical ble controller interrupt 0x0000_0058 7 init 0 settable watchdog interrupt 0x0000_005c 8 init 0 settable reserved 0x0000_0060 9 init 0 settable reserved 0x0000_0064 10 init 0 settable reserved 0 x0000_0068 11 init 0 settable reserved 0x0000_006c 12 init 0 settable reserved 0x0000_0070 13 init 0 settable adc interrupt 0x0000_0074 14 init 0 settable i2c 2 interrupt 0x0000_0078 15 init 0 settable i2c 1 interrupt 0x0000_007c 16 init 0 settable r eserved 0x0000_0080 17 init 0 settable mft1 a interrupt 0x0000_0084 18 init 0 settable mft1 b interrupt 0x0000_0088 19 init 0 settable mft2 a interrupt 0x0000_008c 20 init 0 settable mft2 b interrupt 0x0000_0090 21 init 0 settable rtc interrupt 0x0000 _0094 22 init 0 settable reserved 0x0000_0098 23 init 0 settable dma interrupt 0x0000_009c 24 C 31 init 0 settable reserved 0x0000_00a0 C 0x0000_00bc
functional details bluenrg - 1 16 / 173 docid028866 rev 1 3.3 memories the memory subsystem consists of 160 kb flash memory and two banks of 12 kb ultra - low leakage static ram blocks. the 160 kb flash memory is available to the user and can be accessed per 32 - bit for read access and per 32 - bit for write access (with 4x32 - bit fifo). the access to the static ram can be as bytes, half words (16 bits) or words (32 bits). a 12 kb ram block is always in retention mode, whereas the second 12 kb ram block is switchable and can be put in retention mode according to the user needs. 3.4 power management the bluenrg - 1 integrates both a low dropout voltage regulator (ldo) and a step - down dc - dc converter to supply the internal bluenrg - 1 circuitry. the bluenrg - 1 most efficient power management configuration is with dc - dc converter active where best power consumption is obtained without co mpromising performances. nevertheless, a configuration based on ldo can also be used, if needed. a simplified version of the state machine is shown below. figure 4 : bluenrg - 1 power management state machine 3.4.1 states description 3.4.1.1 preactive state the preactive state is the default state after a por event. in this state: ? all the digital power supplies are stable. ? the high frequency clock runs on internal fast clock rc oscillator (16 mhz). ? th e low frequency clock runs on internal rc oscillator (32.768 khz).
bluenrg - 1 functional detail s docid028866 rev 1 17 / 173 3.4.1.2 active state in this state: ? the high frequency runs on the accurate clock (16 mhz 50 ppm) provided by the external xo. the internal fast clock ro oscillator is swi tched off. if the external xo is at 32 mhz, some specific programming are needed, see section 8.5.3: "switching to external clock" . 3.4.1.3 standby state in this state: ? only the digital power supplies ne cessary to keep the ram in retention are used. the wake - up from this low power state is driven by the following sources: ? io9 ? io10 ? io11 ? io12 ? io13 if they have been programmed as wake - up source in the system controller registers. 3.4.1.4 sleep state in this state: ? only the digital power supplies necessary to keep the ram in retention are used. ? the low frequency oscillator is switched on. the wake - up from this low power state is driven by the following sources: ? io9 ? io10 ? io11 ? io12 ? io13 if they have been programmed as wake - up source in the system controller registers and from the internal timers of the ble radio. 3.4.2 power saving strategy the application power saving strategy is based on clock stopping, dynamic clock gating, di gital power supply switch off and analog current consumption minimization. a summary of functional blocks versus the bluenrg - 1 states is provided below. table 3: relationship between bluenrg - 1 states and functional blocks reset standby sleep preactive act ive lockrx/ lock tx rx tx ldo_soft_1v2 or ldo_soft_0v9 off on on on on on on on ldo_strong_1v2 off off off on on on on on
functional details bluenrg - 1 18 / 173 docid028866 rev 1 reset standby sleep preactive act ive lockrx/ lock tx rx tx ldo_dig_1v8 off off off on on on on on smps off off off on on on on on ldo_dig_1v2 off off off on on on on on bor off on on on o n on on on 16 mhz ro off off off on off off off off 16 mhz xo off off off off on on on on 32 khz ro or xo off off on on on on on on 3.4.3 system controller registers system_ctrl peripheral base address (system_ctrl_base_addr) 0x402000 00. table 4: system_ctrl registers address offset name rw reset description 0x00 wkp_io_is rw 0x00000000 level selection for wakeup io (1 bit for io). 0: the system wakes up when io is low. 1: the system wakes up when io is high. 0x04 wkp_io_ie rw 0x0000 0007 enables the io that wakes up the device (1 bit for io). 0: the wakes up feature on the io is disabled. 1: the wakes up feature on the io is enabled. 0x08 ctrl rw 0x00000000 xo frequency indication is provided by the application. refer to the detailed description below. table 5: system_ctrl - wkp_io_is register description: address offset system_ctrl_base_addr+0x00 bit field name reset rw description 4:0 level_sel 0x00 rw selects the active wake up level for the five ios. 0: the system wakes up when io is low. 1: the system wakes up when io is high. one bit by io: ? bit0: io9 ? bit1: io10 ? bit2: io11 ? bit3: io12 ? bit4: io13 31:5 reserved 0x00 r reserved
bluenrg - 1 functional details docid028866 rev 1 19 / 173 table 6: system_ctrl - wkp_io_ie register description: address offset system_ctrl_base_addr+0x04 bit field name reset rw description 4:0 io_wakeup_en 0x07 rw enables the ios to be wake up source. 0: wake up on the io disabled. 1: wake up on the io enabled. one bit by io: ? bit0: io9 ? bit1: io10 ? bit2: io11 ? bit3: io12 ? bit4: io13 31:5 reserved 0x00 r reserve d table 7: system_ctrl - ctrl register description: address offset system_ctrl_base_addr+0x08 bit field name reset rw description 0 mhz32_sel 0x0 rw indicates the crystal frequency used in the application. 0: the 16 mhz is selected. 1: the 32 mhz is sel ected. 31:1 reserved 0x0 r reserved ahbupconv peripheral base address (ahbupconv_base_addr) 0x40c00000. table 8: ahbupconv registers address offset name rw reset description 0x00 command rw 0x00000000 ahb up/down converter command register blue_ctrl peripheral base address (blue_ctrl_base_addr) 0x40800000. table 9: blue_ctrl registers address offset name rw reset description 0x04 timeout rw 0x00000000 timeout programming register 0x0c radio_config rw 0x00000000 radio configuration register
functional details bluenrg - 1 20 / 173 docid028866 rev 1 3.5 clock s and reset management the bluenrg - 1 embeds an rc low - speed frequency oscillator at 32 khz and an ro high - speed frequency oscillator at 16 mhz. the low - frequency clock is used in low power mode and can be supplied either by a 32.7 kh z oscillator that uses an external crystal and guarantees up to 50 ppm frequency tolerance, or by a ring oscillator with maximum 500 ppm frequency tolerance, which does not require any external components. the primary high - speed frequency clock is a 16 m hz or 32 mhz crystal oscillator. a fast - starting 16 mhz ring oscillator provides the clock while the crystal oscillator is starting up. frequency tolerance of high - speed crystal oscillator is 50 ppm. the usage of the 16 mhz (or 32 mhz) crystal is strictly necessary for rf communications. the clock tree for the peripherals is as follows: figure 5 : clock tree when 32 mhz xo is used, only the cortex - m0, the dma and the apb tree (except for ble radio access) runs at 32 mhz. the re st of the clock tree is divided by two and stays at 16 mhz. the following clocks can be enabled/disabled by software to implement optimal power consumption: ? dma ? ble controller ? ble clock generator ? rng ? flash controller ? gpio ? system controller ? uart ? spi ? i2c1 ? i2c2
bluenrg - 1 functional details docid028866 rev 1 21 / 173 ? adc ? mft1 ? mft2 ? rtc ? wdg by default all peripherals apb clock are enabled. the following clocks are enabled/disabled automatically: ? processor clock (disabled in sleep mode) ? ram clock (disabled if processor clock, spi clock and ble clock are all disa bled) 3.5.1 reset management figure 6: "reset and wakeup generation" shows the general principle of reset. releasing the reset pin puts the chip out of shutdown state. the wakeup logic is powered and receiv es the por. each time the wake - up controller decides to exit sleep or standby modes, it will generate a reset for the core logic. the core logic can also be reset by: ? watchdog ? reset request from the processor (system reset) ? lockup state of the cortex - m0. the swd logic is reset by the por. it is important to highlight that reset pin actually power down chip, so it is not possible to perform debug access with system under reset. figure 6 : reset and wakeup generation 3.5.1.1 power - on - rese t the power - on - reset (por) signal is the combination of the por signal and the bor signal generated by the analog circuitry contained in the bluenrg - 1 device. the combination of these signals is used to generate the input to the cort ex - m0 which is used to reset the debug access port (dap) of the processor. it is also used to generate the signal which resets the debug logic of the cortex - m0. the por signal also resets the tap controller of the bluenrg - 1 and a part of the flash controll er (managing the flash memory boot, which does not need to be impacted by system resets).
functional details bluenrg - 1 22 / 173 docid028866 rev 1 3.5.1.2 watchdog reset the bluenrg - 1 contains a watchdog timer, which may be used to recover from software crashes. the watchdog contains a 32 - bit down counter, which generates an interrupt, if the interrupt is not serviced, the watchdog will generate a reset. the watchdog reset will reset the flash controller, the cortex - m0 and all its peripherals but it will not reset the debug circuitry of the cortex - m0. 3.5.1.3 system reset request the system reset request is generated by the debug circuitry of the cortex - m0. the debugger writes to the sysresetreq bit of the application interrupt and reset control register (aircr). this system reset r equest through aircr register can also be done by embedded software. the system reset request does not affect the debugger, thus allowing the debugger to remain connected during the reset sequence. 3.5.1.4 lockup reset the cortex - m0 generate s an output lockup that indicates that the core is in the architected lock - up state resulting from an unrecoverable exception. the lockup signal is used to generate reset in the bluenrg - 1. this reset will affect the cortex - m0, the flash controller, and all the peripherals. the lockup signal does not reset the cortex - m0 debug circuitry. 3.5.2 reset and wakeup reason decoding the bluenrg - 1 provides a set of registers to identify the reason behind a reset and wakeup generation. two registers a re used: ckgen_soc - >reason_rst and ckgen_ble - >reason_rst. the possible reasons are listed below: 1. if the register ckgen_soc - >reason_rst = 0, according to the ckgen_ble - >reason_rst the possible reasons are: a. wakeup from io9, io10, io11, io12, io13. b. wakeup fro m internal timer: ble timer 1 or ble timer 2. c. por or bor 2. if the register ckgen_soc - >reason_rst is not 0, according to its value the possible reasons are: a. system reset b. watchdog reset c. lockup reset. 3.5.3 switching to external clock when the system is in preactive state (run from internal ro 16 mhz), the software sequence to switch to active should include switch to external xo. when the system uses an external xo at 32 mhz instead of 16 mhz, the following steps need to be done: 1. in preactive state, operate as follow routine: uint8_t config[] = { 0x02, 0x3a, 0x44, 0x00}; blue_ctrl - >radio_config = 0x10000 | (uint16_t) ( (uint32_t)config & 0x0000ffff ); while((blue_ctrl - >radio_config & 0x10000) != 0); 1. set the bitfield mhz32_sel of register system_ctrl, for the digital part. 2. wait the state machine is in active state by using the follow routine:
bluenrg - 1 functional details docid028866 rev 1 23 / 173 uint32_t fsm_status; uint16_t cnt_time = 0; do { cnt_time++; fsm_status = 0x00004382; blue_ctrl - >radio_config = 0x10000 | (uint16_t) ( ( (uint32_t)(&fsm_status) ) & 0x0000ffff); while((blue_ctrl - >radio_config & 0x10000) != 0); } while(((fsm_status>>16) != 0x05) && (cnt_time<1000)); 1. after switching to active state (and not before), write 0x15 in the command register of ahbupconv peripheral. around 10 system clock cycles after this last write, the system will run at 32 mhz except for specific blocks requiring a fixed 16 mhz. the application can make the bus and the core run to 16 mhz by writing 0x14 in the command r egister of ahbupconv peripheral. 3.5.4 clock and reset registers ckgen_soc peripheral base address (ckgen_soc_base_addr) 0x40900000. table 10: ckgen_soc registers address offset name rw reset description 0x00 control rw 0x01fa03f0 contr ol clock and reset of soc. refer to the detailed description below. 0x08 reason_rst r 0x00000000 indicates the reset reason from cortex - m0. refer to the detailed description below. 0x1c die_id r 0x00000110 identification information of the device. refer to the detailed description below. 0x20 clock_en rw 0x0003ffff enable or gates the apb clock of the peripherals. refer to the detailed description below. 0x24 dma_config rw 0x00000000 dma config. refer to the detailed description below. table 11: ckgen _soc - control register description: address offset ckgen_soc_base_addr+0x00 bit field name reset rw description 9:0 reserved 0x3f0 r reserved 13:10 uart_ckdiv 0x0 rw uart baud rate clock setting from 1 to 16 mhz according to the formula 16 / (n + 1) mhz . 31:14 reserved 0x007e8 r reserved
functional details bluenrg - 1 24 / 173 docid028866 rev 1 table 12: ckgen_soc - reason_rst register description: address offset ckgen_soc_base_addr+0x08 bit field name reset rw description 0 reserved 0x0 r reserved 1 sysreq 0x0 r reset caused by cortex - m0 debug asserting s ysresetreq 2 wdg 0x0 r reset caused by assertion of watchdog reset 3 lockup 0x0 r reset caused by cortex - m0 asserting lockup signal 31:4 reserved 0x0 r reserved table 13: ckgen_soc - die_id register description: address offset ckgen_soc_base_addr+0x1c bit field name reset rw description 3:0 rev 0x0 r cut revision 8:4 version 0x11 r cut version 11:9 product 0x0 r product 31:12 reserved 0x0 r reserved table 14: ckgen_soc - clock_en register description: address offset ckgen_soc_base_addr+0x20 bit f ield name reset rw description 0 gpio 0x1 rw gpio clock 1 nvm 0x1 rw flash controller clock 2 sysctrl 0x1 rw system controller clock 3 uart 0x1 rw uart clock 4 spi 0x1 rw spi clock 6:5 reserved 0x3 r reserved 7 wdog 0x1 rw watchdog clock 8 adc 0x1 rw adc clock 9 i2c1 0x1 rw i2c1 clock 10 i2c2 0x1 rw i2c2 clock 11 mft1 0x1 rw mft1 clock 12 mft2 0x1 rw mft2 clock 13 rtc 0x1 rw rtc clock 15:14 reserved 0x3 r reserved 16 dma 0x1 rw dma ahb clock 17 rng 0x1 rw rng ahb clock 31:18 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 25 / 173 table 15: ckgen_soc - dma_config register description: address offset ckgen_soc_base_addr+0x24 bit field name reset rw description 0 adc_ch0 0x0 rw select adc on dma channel 0 instead of peripheral 1 adc_ch1 0x0 rw select adc on dma channel 1 instead of peripheral 2 adc_ch2 0x0 rw select adc on dma channel 2 instead of peripheral 3 adc_ch3 0x0 rw select adc on dma channel 3 instead of peripheral 4 adc_ch4 0x0 rw select adc on dma channel 4 instead of peripheral 5 adc_ch5 0x0 rw select adc o n dma channel 5 instead of peripheral 6 adc_ch6 0x0 rw select adc on dma channel 6 instead of peripheral 7 adc_ch7 0x0 rw select adc on dma channel 7 instead of peripheral 31:8 reserved 0x0 r reserved only one dma channel for the adc should be sele cted at time. hardware does not prevent to select more than one dma channel for adc. ckgen_ble peripheral base address (ckgen_ble_base_addr) 0x48100000. table 16: ckgen_ble registers address offset name rw reset description 0x08 reason_rst r 0x00000005 indicates the reset reason from ble. refer to the detailed description below. 0x0c clk32k_count rw 0x0000000f counter of 32 khz clock. refer to the detailed description below. 0x10 clk32k_period r 0x00000000 period of 32 khz clock. refer to the detailed description below. 0x14 clk32k_freq r 0x00000000 measurement of frequency of 32 khz clock. refer to the detailed description below. 0x18 clk32k_it rw 0x00000000 interrupt event for 32 khz clock measurement. refer to the detailed description below. tabl e 17: ckgen_ble - reason_rst register description: address offset ckgen_ble_base_addr+0x08 bit field name reset rw description 0 reserved 0x1 r reserved 1 bor 0x0 r reset from bor 2 por 0x1 r reset from por 3 wkp_io9 0x0 r wakeup from external io9 4 w kp_io10 0x0 r wakeup from external io10 5 wkp_io11 0x0 r wakeup from external io11
functional details bluenrg - 1 26 / 173 docid028866 rev 1 bit field name reset rw description 6 wkp_io12 0x0 r wakeup from external io12 7 wkp_io13 0x0 r wakeup from external io13 8 wkp_blue 0x0 r wakeup coms from the timer 1 expiration in the wakeup control bloc k of the ble radio 10 wkp2_blue 0x0 r wakeup coms from the timer 2 expiration in the wakeup control block of the ble radio 31:11 reserved 0x0 r reserved table 18: ckgen_ble - clk32k_count register description: address offset ckgen_ble_base_addr+0x0c bi t field name reset rw description 8:0 slow_count 0xf rw program the window length (in slow clock period unit) for slow clock measurement 31:9 reserved 0x0 r reserved table 19: ckgen_ble - clk32k_period register description: address offset ckgen_ble_bas e_addr+0x10 bit field name reset rw description 18:0 slow_period 0x0 r indicates slow clock period information. the result provided in this field corresponds to the length of slow_count periods of the slow clock (32 khz) measured in 16 mhz half - period uni t. the measurement is done automatically each time the device enters in active2 mode using slow_count = 16. a new calculation can be launched by writing zero in clk32k_period register. in this case, the time window uses the value programmed in slow_count f ield. 31:19 reserved 0x0 r reserved table 20: ckgen_ble - clk32k_freq register description: address offset ckgen_ble_base_addr+0x14 bit field name reset rw description 26:0 slow_freq 0x0 r value equal to 2^33 / slow_period 31:27 reserved 0x0 r reserve d table 21: ckgen_ble - clk32k_it register description: address offset ckgen_ble_base_addr+0x18 bit field name reset rw description 0 clk32k_meas_irq 0x0 rw when read, provides the status of the interrupt indicating slow lock measurement is finished: 0: no pending interrupt. 1: pending interrupt. when written, clears the interrupt: 0: no effect. 1: clear the interrupt.
bluenrg - 1 functional details docid028866 rev 1 27 / 173 bit field name reset rw description 31:1 reserved 0x0 r reserved 3.6 adc 3.6.1 introduction the bluenrg - 1 integrates a 10 - bit analog - t o - digital converter (adc) for sampling an external signal. main features are: ? sampling frequency 1 mhz ? one channel in single ended or differential input through the pins adc1 and adc2 ? battery level conversion ? the conversion are either continuous or single step acquisition ? an integrated digital filter is used to process a pdm data stream from a mems microphone 3.6.2 functional overview the figure below shows a top diagram of the adc. figure 7 : block diagram of adc several channels are available for conversion, the chsel selects the channel according to . table 22: adc channels chsel channels description 0 all switch open. no input 1 single ended through adc2 pin. inp = vbias (inte rnal), inn = adc2 pin 2 single ended through adc1 pin. inp = adc1 pin, inn = vbias (internal) 3 differential adc1 pin C adc2 pin. inp = adc1 pin, inn = adc2 pin 5 battery level detector. inn = bld, inp = 0.6 v (internal) 6 short. inp = inn = 0.6 v (int ernal)
functional details bluenrg - 1 28 / 173 docid028866 rev 1 the conversion can be single (cont = 0) or continuous (cont = 1). in continuous mode, the conversion runs with a preprogrammed sampling rate, while in single step mode the adc performs a conversion and then stops. the output data rate depends on d ecim_rate according to the table below. table 23: adc data rate decim_rate output data rate [ksample/s] 0 (200) 5 1 (100) 10 2 (64) 15.625 3 (32) 31.25 the system can work in conjunction with an external mems microphone by setting mic_sel. in this mo de, an io configured as pdm_clk provides the clock to the external microphone, while an io configured as pdm_data received the pdm stream from the external microphone. the external clock is 1.6 mhz (dig_filt_clk = 0) or 0.8 mhz (dig_filt_clk = 1). the outp ut data rate changes with decim_rate according to table 24: "adc data rate with microphone mode" . table 24: adc data rate with microphone mode dig_filt_clk decim_rate output data rate [ksample/s] 1 (clock = 0.8 mhz) 0 (200 ) 4 1 (100) 8 2 (64) 12.5 3 (32) 25 0 (clock = 1.6 mhz) 0 (200) 8 1 (100) 16 2 (64) 25 3 (32) 50 3.6.2.1 adc start conversion the adc both analog and digital sub - system are switched on by setting adcon and swstart. the convers ion operation consists of four phases. 1. the wake - up phase lasts 5 us, is present at the beginning of a single acquisition, with the goal to let the analog system to settle before to start the acquisition. 2. if the calen is set, a calibration phase is perform ed. it permits to compensate the offset in the analog part. the conversion status is tracked by sr status register. at the beginning of the conversion the busy bit is set and masks any attempt to change conf, up to the end of the conversion. at end of this conversion, the endcal flag is generated and the offset register is written with the converted offset voltage. 3. the acquisition phase is regulated by a timeout depending on the resolution. in this phase, digital filter chain processes the data coming from adc.
bluenrg - 1 functional details docid028866 rev 1 29 / 173 4. the elaboration phase is at the end of the timeout, the data obtained at the output of the digital filter is written in the data register. if the calibration is on, the output of the digital filter is de - embedded considering the content of the offset register. furthermore, the adceoc flag is generated to warn about the end of conversion. if enab_comp bit is set, the wdog flag is generated to warn that the result of the conversion is between a high threshold_hi and low threshold threshold_lo. 3.6.2.2 adc offset the adc can correct automatically the offset and the gain error. to enable the automatic offset correction the calen and the offset_update must be set. the result of the last calibration is stored in the offset register. the correct ion of the offset can be also done manually, for example by making a conversion of the internal channel inp = inn = 0.6 v and after that, writing the result of conversion in the offset register. 3.6.2.3 adc conversion the relationship betwee n input voltage and adc output code is the follows. single input adc1 pin. single input adc2 pin. differential input (adc1 pin - adc2 pin). where the register refsel (0.0 v, 0.4 v, 0.6 v, 1.2 v) gives vbias. the register pgasel is the input attenua tion. k adc and n is as below: battery level detector. ? 2 1 = ( + 1 ) ? 0 . 6 ? 1 ? + ( ? 0 . 6 ) bias ? 2 2 = ( + 1 ) ? ( 0 . 6 ? 1 + + ( ? 0 . 6 ) ) bias with the register round16 set = k = 1.12 adc n = 15 with the register round16 set = k = 1.68 adc n = 31 adc12 adc1 adc2 vo lt age = vo l t - vo l t 12 = ? ( + 1 ) ? 2 . 4 2 ?
functional details bluenrg - 1 30 / 173 docid028866 rev 1 3.6.3 adc registers adc peripheral base address (adc_base_addr) 0x40800000. table 25: adc registers address offset name rw reset description 0x00 ctrl rw 0x00000000 adc control reg ister. refer to the detailed description below. 0x04 conf rw 0xffffffff adc configuration register. refer to the detailed description below. 0x08 irqstat r 0x00000000 irq masked status register. refer to the detailed description below. 0x0c irqmask rw 0 x0000000f it sets the mask for adc interrupt. refer to the detailed description below. 0x14 data_conv r 0x00000000 result of the conversion in two complement format: ? if round16 = 0: result is mapped on all 32 - bit (can be truncated with loss of dataout[30: 15]) ? if round16 = 1: result is mapped on 16 - bit (can be truncated with loss of dataout[15:0]) 0x18 offset rw 0x00000000 offset for correction of converted data 0x20 sr_reg rw 0x00000000 adc status register. refer to the detailed description below. 0x24 threshold_hi rw 0xffffffff high threshold for window comparator 0x28 threshold_lo rw 0x00000000 low threshold for window comparator table 26: adc - ctrl register description: address offset adc_base_addr+0x00 bit field name reset rw description 0 on 0x 0 rw starts adc analog subsystem. this bit must be set before starting a conversion. 0: adc is off. 1: adc is on. 1 calen 0x0 rw enables the calibration phase when set to 1. this bit is cleared and the calibration is disabled by setting the rstcalen bit. 2 swstart 0x0 rw starts the adc conversion phase when set. 3 reset 0x0 rw reset all the adc registers when set. = 4 . 36 ? ( 1 ? 0 . 622 ) + 2 . 7
bluenrg - 1 f unctional details docid028866 rev 1 31 / 173 bit field name reset rw description 4 stop 0x0 rw permits to stop the continuous conversion. 0: continuous conversion is enabled but swstart and adcon bits must be set. 1: stop the continuous conversion and switch off the adc. 5 enab_comp 0x0 rw enables the window comparator when set to 1. wdog flag is adc_sr register is set if the converted value is between threshold_hi and threshold_lo value. 6 rstcalen 0x0 rw disable the cal ibration phase when set to 1. this bit has to be set to disable the calibration each time calibration is enabled. 7 auto_offset 0x0 rw enables the update of offset register. 0: offset register is not updated. 1: offset register is updated. 8 mic_on 0x0 r w enables the filter chain for voice when set to 1. 0: filter chain is disabled. 1: filter chain is enabled. 9 dma_en 0x0 rw enables the dma. 0: dma is disabled. 1: dma is enabled. 31:10 reserved 0x0 r reserved table 27: adc - conf register description : address offset adc_base_addr+0x04 bit field name reset rw description 0 en_dfmode 0x1 rw control the current in differential mode: 0: differential mode with dc common mode current not nulled. 1: differential mode with dc common mode current nulled. 3:1 chsel 0x7 rw select the input channel: 000b: all switches open. 001b: single ended through adc2 pin. inp = vbias (internal), inn = adc2 pin. 010b: single ended through adc1 pin. inp = adc1 pin, inn = vbias (internal). 011b: differential adc1 pin - adc2 pi n, inp = adc1 pin, inn = adc2 pin. 101b: battery level detector. inp = 0.6 v (internal), inn = bld. 110b: short inn = inp = 0.6 v (internal). 5:4 refsel 0x3 rw set the vbias for single ended conversion: 00b: 0.0 v. 01b: 0.4 v. 10b: 0.6 v. 11b: 1.2 v.
functional details bluenrg - 1 32 / 173 docid028866 rev 1 bit field name reset rw description 7:6 decim_rate 0x3 rw set the adc resolution: 00b: set the decimation factor to 200. 01b: set the decimation factor to 100. 10b: set the decimation factor to 64. 11b: set the decimation factor to 32. 9:8 pgasel 0x3 rw set the input attenuator value: 000b: in put attenuator at 0 db. 001b: input attenuator at 6.02 db. 010b: input attenuator at 9.54 db. 10 reserved 0x1 r reserved 11 cont 0x1 rw enable the continuous conversion mode: 0: single conversion. 1: continuous conversion. 16:12 reserved 0x1f r reserved 17 round16 0x1 rw result mapped on 32 or 16 bits: 0: output result mapped to 32 bits. 1: output result mapped to 16 bits. 18 skip 0x1 rw it permits to bypass the filter comb to speed up the conversion for signal at low frequency: 0: filter for comb not bypassed. 1: filter for comb bypassed. 19 reserved 0x1 r reserved 20 dig_filt_clk 0x1 rw frequency clock selection value on gpio0 when mic_sel=1: 0: 0.8 mhz. 1: 1.6 mhz. 21 dis_wkp_wait 0x1 rw disable the wake - up timer before to start the conversion fro m input: 0: do not disable the wake up time before conversion. 1: disable the wake up time before conversion. 22 mic_sel 0x1 rw provides the clock on gpio: 0: do not provided any external clock source. 1: provide clock source from gpio. 31:23 reserved 0x 1ff r reserved table 28: adc - irqstat register description: address offset adc_base_addr+0x08 bit field name reset rw description 0 endcal 0x0 r 1: when the calibration is completed. clear on register read. 1 busy 0x0 r 1: during conversion. clear on register read if busy condition no more active. 2 eoc 0x0 r 1: when the conversion is completed. clear on register read. 3 wdog 0x0 r 1: when the data is within the thresholds. clear on register read.
bluenrg - 1 functional details docid028866 rev 1 33 / 173 bit field name reset rw description 31:4 reserved 0x0 r reserved table 29: adc - irqma sk register description: address offset adc_base_addr+0x0c bit field name reset rw description 0 endcal 0x1 rw interrupt mask for the end of calibration event: 0: interrupt is enabled. 1: interrupt is disabled. 1 busy 0x1 rw interrupt mask for the adc b usy event: 0: interrupt is enabled. 1: interrupt is disabled. 2 eoc 0x1 rw interrupt mask for the end of conversion event: 0: interrupt is enabled. 1: interrupt is disabled. 3 wdog 0x1 rw interrupt mask for the within the threshold event: 0: interrupt is enabled. 1: interrupt is disabled. 31:4 reserved 0x0 r reserved table 30: adc - data_conv register description: address offset adc_base_addr+0x14 bit field name reset rw description 31:0 data_conv 0x00000000 r result of the conversion in two complemen t format: ? if round16 = 0: result is mapped on all 32 - bit (can be truncated with loss of data_conv[30:15]). ? if round16 = 1: result is mapped on 16 - bit (can be truncated with loss of data_conv [15:0]). table 31: adc - offset register description: address o ffset adc_base_addr+0x18 bit field name reset rw description 31:0 offset 0x00000000 rw offset for correction of converted data. table 32: adc - sr_reg register description: address offset adc_base_addr+0x20 bit field name reset rw description 0 endcal 0x0 rw 1: when the calibration is completed. the result of the calibration is written in the offset register. 1 busy 0x0 rw 1: during conversion. 2 eoc 0x0 rw 1: when the conversion is completed. 3 wdog 0x0 rw if enab_comp = 1, this bit indicates the re sult of the conversion is between high and low threshold: 0: dataout[31:0] is not between threshold_hi and threshold_lo values. 1: dataout[31:0] is between threshold_hi and threshold_lo values. 31:4 reserved 0x0 r reserved
functional details bluenrg - 1 34 / 173 docid028866 rev 1 table 33: adc - threshold_hi r egister description: address offset adc_base_addr+0x24 bit field name reset rw description 31:0 threshold_hi 0xffffffff rw high threshold for window comparator. table 34: adc - threshold_lo register description: address offset adc_base_addr+0x28 bit fie ld name reset rw description 31:0 threshold_lo 0x00000000 rw low threshold for window comparator. 3.7 dma 3.7.1 introduction the bluenrg - 1 device embeds a dma allowing various combination of data transfer between the memory and the peripherals without cpu intervention. main features are: ? eight independently configurable channels connected to dedicated hardware dma requests; software trigger is also supported. ? priorities between requests from channels of the dma are so ftware programmable (four levels consisting of very high, high, medium, low). when two channels with same software priority need attention, channel with lower hardware index will take priority. ? independent source and destination transfer size (byte, half w ord, word), emulating packing and unpacking. ? support for circular buffer management. ? event flags (dma half transfer, dma transfer complete), logically ored together in a single interrupt request for each channel. ? memory - to - memory transfer (ram only), peri pheral - to - memory and memory - to - peripheral, and peripheral - to - peripheral transfers. ? programmable number of data to be transferred up to 65536 bytes. 3.7.2 functional overview the dma controller performs direct memory transfer by sharing the system bus with the other masters of the device. the dma request may stop the cpu access to the system bus for some bus cycles, when the cpu and dma are targeting the same destination (memory or peripheral). the bus matrix implements round - robin schedulin g, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the cpu. 3.7.2.1 dma transactions after an event, the peripheral sends a request signal to the dma controller. the dma controller serves the reque st depending on the channel priorities. as soon as the dma controller accesses the peripheral, the dma controller sends an acknowledge to the peripheral. the peripheral releases its request as soon as it gets the acknowledge from the dma controller. once t he request is deasserted by the peripheral, the dma controller releases the acknowledge. if there are more requests, the peripheral can initiate the next transaction. in summary, each dma transfer consists of three operations:
bluenrg - 1 functional details docid028866 rev 1 35 / 173 ? the loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. the start address used for the first transfer is the base peripheral/memory address programmed in the dma_cparx or dma_cmarx registe r ? the storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. the start address used for the first transfer is the base peripheral/memory address programme d in the dma_cparx or dma_cmarx register ? the post - decrementing of the dma_cndtrx register, which contains the number of transactions that have still to be performed. 3.7.2.2 arbiter the arbiter manages the channel requests based on their pri ority and launches the peripheral/memory access sequences. the priorities are managed in two stages: ? software: each channel priority can be configured in the dma_ccrx register. there are four levels: ? very high priority ? high priority ? medium priority ? low pri ority ? hardware: if two requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. for example, channel 2 gets priority over channel 4. 3.7.2.3 dma channels each channel can handle dma transfer between a peripheral register located at a fixed address and a memory address. the amount of data to be transferred (up to 65535) is programmable. the register, which contains the amount of data items to be transferred , is decremented after each transaction. programmable data sizes transfer data sizes of the peripheral and memory are fully programmable through the psize and msize bits in the dma_ccrx register. pointer increments peripheral and memory pointers can option ally be automatically post - incremented after each transaction depending on the pinc and minc bits in the dma_ccrx register. if incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 de pending on the chosen data size. the first transfer address is the one programmed in the dma_cparx/dma_cmarx registers. during transfer operations, these registers keep the initially programmed value. the current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. if the channel is configured in noncircular mode, no dma request is served after the last transfer (that is once the number of data items to be transferred has reached zero). in order to reload a new number of data items to be transferred into the dma_cndtrx register, the dma channel must be disabled. if a dma channel is disabled, the dma registers are not reset. the dma channel registers (dma_ccrx, dma_cparx and dma_cmarx) retain the init ial values programmed during the channel configuration phase.
functional details bluenrg - 1 36 / 173 docid028866 rev 1 in circular mode, after the last transfer, the dma_cndtrx register is automatically reloaded with the initially programmed value. the current internal address registers are reloaded with the bas e address values from the dma_cparx/dma_cmarx registers. channel configuration procedure the following sequence should be followed to configure a dma channelx (where x is the channel number). 1. set the peripheral register address in the dma_cparx register. t he data will be moved from/ to this address to/ from the memory after the peripheral event. 2. set the memory address in the dma_cmarx register. the data will be written to or read from this memory after the peripheral event. 3. configure the total number of dat a to be transferred in the dma_cndtrx register. after each peripheral event, this value will be decremented. 4. configure the channel priority using the pl[1:0] bits in the dma_ccrx register. 5. configure data transfer direction, circular mode, peripheral & memo ry incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the dma_ccrx register. 6. activate the channel by setting the enable bit in the dma_ccrx register. as soon as the channel is enabled, it can serve any dma req uest from the peripheral connected on the channel. once half of the bytes are transferred, the half - transfer flag (htif) is set and an interrupt is generated if the half - transfer interrupt enable bit (htie) is set. at the end of the transfer, the transfer complete flag (tcif) is set and an interrupt is generated if the transfer complete interrupt enable bit (tcie) is set. circular mode circular mode is available to handle circular buffers and continuous data flows (e.g. adc scan mode). this feature can be e nabled using the circ bit in the dma_ccrx register. when circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the dma requests continue to b e served. memory - to - memory mode the dma channels can also work without being triggered by a request from a peripheral. this mode is called memory - to - memory mode. if the mem2mem bit in the dma_ccrx register is set, then the channel initiates transfers as so on as it is enabled by software by setting the enable bit (en) in the dma_ccrx register. the transfer stops once the dma_cndtrx register reaches zero. memory - to - memory mode may not be used at the same time as circular mode.
bluenrg - 1 functional details docid028866 rev 1 37 / 173 3.7.2.4 programmable data width, data alignment and endianness when psize and msize are not equal, the dma performs some data alignments as described in table 35: "programmable data width and endian behavior (when bits pinc = minc = 1)" : programmable data width & endian behavior (when bits pinc = minc = 1). table 35: programmable data width and endian behavior (when bits pinc = minc = 1) source port width destination port width number of data items to transfer (ndt) source content: addres s/data transfer operations destination content: address/data 8 8 4 @0x0 / b0 1: read b0[7:0] @0x0 then write b0[7:0] @0x0 @0x0 / b0 @0x1 / b1 2: read b1[7:0] @0x1 then write b0[7:0] @0x1 @0x1 / b1 @0x2 / b2 3: read b2[7:0] @0x2 then write b0[7:0] @0x2 @0x2 / b2 @0x3 / b3 4: read b3[7:0] @0x3 then write b0[7:0] @0x3 @0x3 / b3 8 16 4 @0x0 / b0 1: read b0[7:0] @0x0 then write 00b0[15:0] @0x0 @0x0 / 00b0 @0x1 / b1 2: read b1[7:0] @0x1 then write 00b0[15:0] @0x2 @0x2 / 00b1 @0x2 / b2 3: rea d b2[7:0] @0x2 then write 00b0[15:0] @0x4 @0x4 / 00b2 @0x3 / b3 4: read b3[7:0] @0x3 then write 00b0[15:0] @0x6 @0x6 / 00b3 8 32 4 @0x0 / b0 1: read b0[7:0] @0x0 then write 000000b0[31:0] @0x0 @0x0 / 000000b0 @0x1 / b1 2: read b1[7:0] @0x1 then wr ite 000000b0[31:0] @0x4 @0x4 / 000000b1 @0x2 / b2 3: read b2[7:0] @0x2 then write 000000b0[31:0] @0x8 @0x8 / 000000b2 @0x3 / b3 4: read b3[7:0] @0x3 then write 000000b0[31:0] @0xc @0xc / 000000b3 16 8 4 @0x0 / b1b0 1: read b1b0[15:0] @0x0 then wri te b0[7:0] @0x0 @0x0 / b0
functional details bluenrg - 1 38 / 173 docid028866 rev 1 source port width destination port width number of data items to transfer (ndt) source content: addres s/data transfer operations destination content: address/data @0x1 / b3b2 2: read b3b2[15:0] @0x2 then write b0[7:0] @0x1 @0x1 / b2 @0x2 / b5b4 3: read b5b4[15:0] @0x4 then write b0[7:0] @0x2 @0x2 / b4 @0x3 / b7b6 4: read b7b6[15:0] @0x6 then write b0[7:0] @0x3 @0x3 / b6 16 16 4 @0x0 / b1b0 1: read b1b0[15:0] @0x0 then write b1b0[15:0] @0x0 @0x0 / b1b0 @0x1 / b3b2 2: read b3b2[15:0] @0x2 then write b3b2[15:0] @0x2 @0x2 / b3b2 @0x2 / b5b4 3: read b5b4[15:0] @0x4 then write b5b4[15:0] @0x4 @0x4 / b5b4 @0x3 / b7b6 4: rea d b7b6[15:0] @0x6 then write b7b6[15:0] @0x6 @0x6 / b7b6 16 32 4 @0x0 / b1b0 1: read b1b0[15:0] @0x0 then write 0000b1b0[31:0] @0x0 @0x0 / 0000b1b0 @0x1 / b3b2 2: read b3b2[15:0] @0x2 then write 0000b3b2[31:0] @0x4 @0x4 / 0000b3b2 @0x2 / b5b4 3: r ead b5b4[15:0] @0x4 then write 0000b5b4[31:0] @0x8 @0x8 / 0000b5b4 @0x3 / b7b6 4: read b7b6[15:0] @0x6 then write 0000b7b6[31:0] @0xc @0xc / 0000b7b6 32 8 4 @0x0 / b3b2b1b0 1: read b3b2b1b0[31:0] @0x0 then write b0[7:0] @0x0 @0x0 / b0 @0x4 / b7b6b 5b4 2: read b7b6b5b4[31:0] @0x4 then write b0[7:0] @0x1 @0x1 / b4
bluenrg - 1 functional details docid028866 rev 1 39 / 173 source port width destination port width number of data items to transfer (ndt) source content: addres s/data transfer operations destination content: address/data @0x8 / bbbab9b8 3: read bbbab9b8[31:0] @0x8 then write b0[7:0] @0x2 @0x2 / b8 @0xc / bfbebdbc 4: read bfbebdbc[31:0] @0xc then write b0[7:0] @0x3 @0x3 / bc 32 16 4 @0x0 / b3b2b1b0 1 : read b3b2b1b0[31:0] @0x0 then write b1b0[15:0] @0x0 @0x0 / b1b0 @0x4 / b7b6b5b4 2: read b7b6b5b4[31:0] @0x4 then write b3b2[15:0] @0x2 @0x2 / b5b4 @0x8 / bbbab9b8 3: read bbbab9b8[31:0] @0x8 then write b5b4[15:0] @0x4 @0x4 / b9b8 @0xc / bfbeb dbc 4: read bfbebdbc[31:0] @0xc then write b7b6[15:0] @0x6 @0x6 / bdbc 32 32 4 @0x0 / b3b2b1b0 1: read b3b2b1b0[31:0] @0x0 then write 0000b1b0[31:0] @0x0 @0x0 / b3b2b1b0 @0x4 / b7b6b5b4 2: read b7b6b5b4[31:0] @0x4 then write 0000b3b2[31:0] @0x4 @0x4 / b7b6b5b4 @0x8 / bbbab9b8 3: read bbbab9b8[31:0] @0x8 then write 0000b5b4[31:0] @0x8 @0x8 / bbbab9b8 @0xc / bfbebdbc 4: read bfbebdbc[31:0] @0xc then write 0000b7b6[31:0] @0xc @0xc / bfbebdbc the dma is addressed through ahb and can be accessed o nly with 32 - bit access. any 8 - bit or 16 - bit access will generate a hard fault. when the dma initiates an ahb byte or halfword write operation, the data are duplicated on the unused lanes of the hwdata[31:0] bus. so when the used ahb slave peripheral
functiona l details bluenrg - 1 40 / 173 docid028866 rev 1 does n ot support byte or halfword write operations (when hsize is not used by the peripheral) and does not generate any error, the dma writes the 32 hwdata bits as shown in the two examples below: ? to write the halfword 0xabcd, the dma sets the hwdata bus to 0 xabcdabcd with hsize = halfword ? to write the byte 0xab, the dma sets the hwdata bus to 0xabababab with hsize = byte assuming that the ahb/apb bridge is an ahb 32 - bit slave peripheral that does not take the hsize data into account, it will transform an y ahb byte or halfword operation into a 32 - bit apb operation in the following manner: ? an ahb byte write operation of the data 0xb0 to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an apb word write operation of the data 0xb0b0b0b0 to 0x0 ? an ahb half - word write operation of the data 0xb1b0 to 0x0 (or to 0x2) will be converted to an apb word write operation of the data 0xb1b0b1b0 to 0x0 3.7.2.5 error management a dma transfer error can be generated by reading from or writing to a res erved address space. when a dma transfer error occurs during a dma read or a write access, the faulty channel is automatically disabled through a hardware clear of its en bit in the corresponding channel configuration register (dma_ccrx). the channel's tra nsfer error interrupt flag (teif) in the isr register is set and an interrupt is generated if the transfer error interrupt enable bit (teie) in the dma_ccrx register is set. 3.7.2.6 interrupts an interrupt can be produced on a half - transfer, transfer complete or transfer error for each dma channel. separate interrupt enable bits are available for flexibility. table 36: dma interrupt requests interrupt event event flag enable control bit half - transfer htif htie transfer complete tcif tcie t ransfer error teif teie 3.7.2.7 dma request mapping the eight requests from the peripherals (spi, i2cx[1,2] and uart) are multiplexed before entering dma with the adc request. for each channel, the choice between the peripheral and the ad c is done through the dma_config register.
bluenrg - 1 functional details docid028866 rev 1 41 / 173 figure 8 : dma request mapping in bluenrg - 1 3.7.3 dma registers dma peripheral base address (dma_base_addr) 0xa0000000. table 37: dma registers address offset name rw res et description 0x00 isr r 0x00000000 dma interrupt status register. refer to the detailed description below. 0x04 ifcr w 0x00000000 dma interrupt flag clear register. refer to the detailed description below. table 38:
functional details bluenrg - 1 42 / 173 docid028866 rev 1 dma - isr register description: address offset dma_base_addr+0x00 bit field name reset rw description 0 gif0 0x0 r channel 0 global interrupt flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no te, ht or tc event o n channel 0. 1: a te, ht or tc event occurred on channel 0. 1 tcif0 0x0 r channel 0 transfer complete flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer complete (tc) on cha nnel 0. 1: a transfer complete (tc) occurred on channel 0. 2 htif0 0x0 r channel 0 half transfer flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no half transfer (ht) event on channe l 0. 1: a half transfer (ht) event occurred on channel 0. 3 teif0 0x0 r channel 0 transfer error flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer error (te) event on chann el 0. 1: a transfer error (te) occurred on channel 0. 4 gif1 0x0 r channel 1 global interrupt flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no te, ht or tc event on channel 1. 1: a te, ht or tc event occurred on channel 1. 5 tcif1 0x0 r channel 1 transfer complete flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer complete (tc) on channel 1. 1: a tran sfer complete (tc) occurred on channel 1. 6 htif1 0x0 r channel 1 half transfer flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no half transfer (ht) event on channel 1. 1: a half tr ansfer (ht) event occurred on channel 1. 7 teif1 0x0 r channel 1 transfer error flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer error (te) event on channel 1. 1: a transf er error (te) occurred on channel 1. 8 gif2 0x0 r channel 2 global interrupt flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no te, ht or tc event on channel 2. 1: a te, ht or tc eve nt occurred on channel 2. 9 tcif2 0x0 r channel 2 transfer complete flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer complete (tc) on channel 2. 1: a transfer complete (tc ) occurred on channel 2.
bluenrg - 1 functional details docid028866 rev 1 43 / 173 bit field name reset rw description 10 htif2 0x0 r channel 2 half transfer flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no half transfer (ht) event on channel 2. 1: a half transfer (ht) even t occurred on channel 2. 11 teif2 0x0 r channel 2 transfer error flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer error (te) event on channel 2. 1: a transfer error (te) o ccurred on channel 2. 12 gif3 0x0 r channel 3 global interrupt flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no te, ht or tc event on channel 3. 1: a te, ht or tc event occurred on channel 3. 13 tcif3 0x0 r channel 3 transfer complete flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer complete (tc) on channel 3. 1: a transfer complete (tc) occurred on channel 3. 14 htif3 0x0 r channel 3 half transfer flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no half transfer (ht) event on channel 3. 1: a half transfer (ht) event occurred on channel 3. 15 teif3 0x0 r channel 3 transfer error flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer error (te) event on channel 3. 1: a transfer error (te) occurred on ch annel 3. 16 gif4 0x0 r channel 4 global interrupt flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no te, ht or tc event on channel 4. 1: a te, ht or tc event occurred on channel 4. 17 tcif4 0x0 r channel 4 transfer complete flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer complete (tc) on channel 4. 1: a transfer complete (tc) occurred on channel 4. 18 htif4 0x0 r channel 4 half transfer flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no half transfer (ht) event on channel 4. 1: a half transfer (ht) event occurred on channel 4. 19 teif4 0x0 r channel 4 transfer error flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer error (te) event on channel 4. 1: a transfer error (te) occurred on channel 4.
functional details bluenrg - 1 44 / 173 docid028866 rev 1 bit field name reset rw description 20 gif5 0x0 r channel 5 global interrupt flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no te, ht or tc event on channel 5. 1: a te, ht or tc event occurred on channel 5. 21 tcif5 0x0 r channel 5 transfer complete flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer complete (tc) on channel 5. 1: a transfer complete (tc) occurred on channel 5. 22 htif5 0x0 r channel 5 half transfer flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no half transfer (ht) event on channel 5. 1: a half transfer (ht) event occurred on channel 5. 23 teif5 0x0 r channel 5 transfer error flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer error (te) event on channel 5. 1: a transfer error (te) occurred on channel 5. 24 gif6 0x0 r ch annel 6 global interrupt flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no te, ht or tc event on channel 6. 1: a te, ht or tc event occurred on channel 6. 25 tcif6 0x0 r channel 6 t ransfer complete flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer complete (tc) on channel 6. 1: a transfer complete (tc) occurred on channel 6. 26 htif6 0x0 r channel 6 h alf transfer flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no half transfer (ht) event on channel 6. 1: a half transfer (ht) event occurred on channel 6. 27 teif6 0x0 r channel 6 t ransfer error flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer error (te) event on channel 6. 1: a transfer error (te) occurred on channel 6. 28 gif7 0x0 r channel 7 globa l interrupt flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no te, ht or tc event on channel 7. 1: a te, ht or tc event occurred on channel 7. 29 tcif7 0x0 r channel 7 transfer compl ete flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer complete (tc) on channel 7. 1: a transfer complete (tc) occurred on channel 7.
bluenrg - 1 functional details docid028866 rev 1 45 / 173 bit field name reset rw description 30 htif7 0x0 r channel 7 half transfer flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no half transfer (ht) event on channel 7. 1: a half transfer (ht) event occurred on channel 7. 31 teif7 0x0 r channel 7 transfer error flag. this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the ifcr register. 0: no transfer error (te) event on channel 7. 1: a transfer error (te) occurred on channel 7. table 39: dma - ifcr register description : address offset dma_base_addr+0x04 bit field name reset rw description 0 cgif0 0x0 w channel 0 global interrupt flag. this bit is set by software. 0: no effect. 1: clears the gif, teif, htif and tcif flags in the isr register. 1 ctcif0 0x0 w channel 0 t ransfer complete flag. this bit is set by software. 0: no effect. 1: clears the corresponding tcif flag in the isr register. 2 chtif0 0x0 w channel 0 half transfer flag. this bit is set by software. 0: no effect. 1: clears the corresponding htif flag in t he isr register. 3 cteif0 0x0 w channel 0 transfer error flag. this bit is set by software. 0: no effect. 1: clears the corresponding teif flag in the isr register. 4 cgif1 0x0 w channel 1 global interrupt flag. this bit is set by software. 0: no effect. 1: clears the gif, teif, htif and tcif flags in the isr register. 5 ctcif1 0x0 w channel 1 transfer complete flag. this bit is set by software. 0: no effect. 1: clears the corresponding tcif flag in the isr register. 6 chtif1 0x0 w channel 1 half transf er flag. this bit is set by software. 0: no effect. 1: clears the corresponding htif flag in the isr register. 7 cteif1 0x0 w channel 1 transfer error flag. this bit is set by software. 0: no effect. 1: clears the corresponding teif flag in the isr regist er. 8 cgif2 0x0 w channel 2 global interrupt flag. this bit is set by software. 0: no effect. 1: clears the gif, teif, htif and tcif flags in the isr register. 9 ctcif2 0x0 w channel 2 transfer complete flag. this bit is set by software. 0: no effect. 1: clears the corresponding tcif flag in the isr register.
functional details bluenrg - 1 46 / 173 docid028866 rev 1 bit field name reset rw description 10 chtif2 0x0 w channel 2 half transfer flag. this bit is set by software. 0: no effect. 1: clears the corresponding htif flag in the isr register. 11 cteif2 0x0 w channel 2 transfer error flag. th is bit is set by software. 0: no effect. 1: clears the corresponding teif flag in the isr register. 12 cgif3 0x0 w channel 3 global interrupt flag. this bit is set by software. 0: no effect. 1: clears the gif, teif, htif and tcif flags in the isr register . 13 ctcif3 0x0 w channel 3 transfer complete flag. this bit is set by software. 0: no effect. 1: clears the corresponding tcif flag in the isr register. 14 chtif3 0x0 w channel 3 half transfer flag. this bit is set by software. 0: no effect. 1: clears t he corresponding htif flag in the isr register. 15 cteif3 0x0 w channel 3 transfer error flag. this bit is set by software. 0: no effect. 1: clears the corresponding teif flag in the isr register. 16 cgif4 0x0 w channel 4 global interrupt flag. this bit is set by software. 0: no effect. 1: clears the gif, teif, htif and tcif flags in the isr register. 17 ctcif4 0x0 w channel 4 transfer complete flag. this bit is set by software. 0: no effect. 1: clears the corresponding tcif flag in the isr register. 18 chtif4 0x0 w channel 4 half transfer flag. this bit is set by software. 0: no effect. 1: clears the corresponding htif flag in the isr register. 19 cteif4 0x0 w channel 4 transfer error flag. this bit is set by software. 0: no effect. 1: clears the corre sponding teif flag in the isr register. 20 cgif5 0x0 w channel 5 global interrupt flag. this bit is set by software. 0: no effect. 1: clears the gif, teif, htif and tcif flags in the isr register. 21 ctcif5 0x0 w channel 5 transfer complete flag. this bi t is set by software. 0: no effect. 1: clears the corresponding tcif flag in the isr register. 22 chtif5 0x0 w channel 5 half transfer flag. this bit is set by software. 0: no effect. 1: clears the corresponding htif flag in the isr register. 23 cteif5 0 x0 w channel 5 transfer error flag. this bit is set by software. 0: no effect. 1: clears the corresponding teif flag in the isr register.
bluenrg - 1 functional details docid028866 rev 1 47 / 173 bit field name reset rw description 24 cgif6 0x0 w channel 6 global interrupt flag. this bit is set by software. 0: no effect. 1: clears the gif, teif, h tif and tcif flags in the isr register. 25 ctcif6 0x0 w channel 6 transfer complete flag. this bit is set by software. 0: no effect. 1: clears the corresponding tcif flag in the isr register. 26 chtif6 0x0 w channel 6 half transfer flag. this bit is set by software. 0: no effect. 1: clears the corresponding htif flag in the isr register. 27 cteif6 0x0 w channel 6 transfer error flag. this bit is set by software. 0: no effect. 1: clears the corresponding teif flag in the isr register. 28 cgif7 0x0 w chan nel 7 global interrupt flag. this bit is set by software. 0: no effect. 1: clears the gif, teif, htif and tcif flags in the isr register. 29 ctcif7 0x0 w channel 7 transfer complete flag. this bit is set by software. 0: no effect. 1: clears the correspond ing tcif flag in the isr register. 30 chtif7 0x0 w channel 7 half transfer flag. this bit is set by software. 0: no effect. 1: clears the corresponding htif flag in the isr register. 31 cteif7 0x0 w channel 7 transfer error flag. this bit is set by softw are. 0: no effect. 1: clears the corresponding teif flag in the isr register. ? dma_ch0 peripheral base address (dma_ch0_base_addr) 0xa0000008 ? dma_ch1 peripheral base address (dma_ch1_base_addr) 0xa000001c ? dma_ch2 peripheral base address (dma_ch2_base_addr ) 0xa0000030 ? dma_ch3 peripheral base address (dma_ch3_base_addr) 0xa0000044 ? dma_ch4 peripheral base address (dma_ch4_base_addr) 0xa0000058 ? dma_ch5 peripheral base address (dma_ch5_base_addr) 0xa000006c ? dma_ch6 peripheral base address (dma_ch6_base_addr) 0x a0000080 ? dma_ch7 peripheral base address (dma_ch7_base_addr) 0xa0000094 table 40: dma_chx registers address offset name rw reset description 0x00 ccr rw 0x00000000 dma channel configuration register. refer to the detailed description below. 0x04 cndtr rw 0x00000000 dma channel number of data register. refer to the detailed description below. 0x08 cpar rw 0x00000000 dma channel peripheral address register. refer to the detailed description below. 0x0c cmar rw 0x00000000 dma channel memory address registe r. refer to the detailed description below.
functional details bluenrg - 1 48 / 173 docid028866 rev 1 table 41: dma_chx - ccr register description: address offset dma_chx_base_addr+0x00 bit field name reset rw description 0 en 0x0 rw dma channel enable. 0: dma channel disabled. 1: dma channel enabled. 1 tcie 0x0 rw transfer complete interrupt enable. 0: tc interrupt disabled. 1: tc interrupt enabled. 2 htie 0x0 rw half transfer interrupt enable. 0: ht interrupt disabled. 1: ht interrupt enabled. 3 teie 0x0 rw transfer error interrupt enable. 0: te interrupt disabled. 1: te interrupt enabled. 4 dir 0x0 rw data transfer direction. 0: read from peripheral. 1: read from memory. 5 circ 0x0 rw circular mode. 0: circular mode disabled. 1: circular mode enabled. 6 pinc 0x0 rw peripheral increment mode. 0: peripher al increment disabled. 1: peripheral increment enabled. 7 minc 0x0 rw memory increment mode. 0: memory increment disabled. 1: memory increment enabled. 9:8 psize 0x0 rw peripheral size. 00b: size 8 bits. 01b: size 16 bits. 10b: size 32 bits. 11:10 msize 0x0 rw memory size. 00b: size 8 bits. 01b: size 16 bits. 10b: size 32 bits. 13:12 pl 0x0 rw channel priority level. 00b: low priority. 01b: medium priority. 10b: high priority. 11b: very high priority. 14 mem2mem 0x0 rw memory to memory mode. 0: memory to memory mode disabled. 0: memory to memory mode enabled. 31:15 reserved 0x0 r reserved
bluenrg - 1 func tional details docid028866 rev 1 49 / 173 table 42: dma_chx - cndtr register description: address offset dma_chx_base_addr+0x04 bit field name reset rw description 15:0 ndt 0x0 rw number of data to be tran sferred (0 up to 65535). this register can only be written when the channel is disabled. once the channel is enabled, this register is read - only, indicating the remaining bytes to be transmitted. this register decrements after each dma transfer. once the t ransfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto - reload mode. if this register is zero, no transaction can be served whether the channel is enab led or not. 31:16 reserved 0x0 r reserved table 43: dma_chx - cpar register description: address offset dma_chx_base_addr+0x08 bit field name reset rw description 31:0 pa 0x0 rw base address of the peripheral data register from/to which the data will b e read/written. when psize is 01 (16 - bit), the pa[0] bit is ignored. access is automatically aligned to a halfword address. when psize is 10 (32 - bit), pa[1:0] are ignored. access is automatically aligned to a word address. table 44: dma_chx - cmar regist er description: address offset dma_chx_base_addr+0x0c bit field name reset rw description 31:0 ma 0x0 rw base address of the memory area from/to which the data will be read/written. when msize is 01 (16 - bit), the ma[0] bit is ignored. access is automatica lly aligned to a halfword address. when msize is 10 (32 - bit), ma[1:0] are ignored. access is automatically aligned to a word address. 3.8 spi 3.8.1 introduction the bluenrg - 1 integrates a serial peripheral interface co mpatible with motorola standard. main features are: ? maximal supported baud rate is 1 mhz in slave mode and 8 mhz in master mode. ? parallel - to - serial conversion on data written to an internal 32 - bit wide, 16 - location deep transmitter fifo. ? serial - to - parallel conversion on received data, buffering in a 32 - bit wide 16 - location deep receive fifo. ? programmable data frame size from 4 - bit to 32 - bit. ? programmable clock bit rate and prescaler. ? programmable clock phase and polarity in spi mode. ? support for direct memo ry access (dma).
functional details bluenrg - 1 50 / 173 docid028866 rev 1 3.8.2 functional overview the spi performs serial - to - parallel conversion on data received from a peripheral device on the spi_rx pin, and parallel - to - serial conversion on data written by cpu for transmission on the spi_tx pin. the transmit and receive paths are buffered with internal fifo memories allowing up to 16 x 32 - bit values to be stored independently in both transmit and receive modes. fifos may be burst - loaded or emptied by the system processor or by the dma, from one to eight words per transfer. each 32 - bit word from the system fills one entry in fifo. the spi includes a programmable bitrate clock divider and prescaler to generate the serial output clock signal from the spi_clk pin. 3.8.2.1 spi clock phase and clock polari ty the sph control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture e dge. the spo bit selects the clock polarity (low or high) of the clock signal. sph in conjunction with the spo bit allow four possible timing variations listed in the following table. table 45: spi clock phase and clock polarity sph spo color scheme 0b 0b the clock signal is stopped to low inactive level between transfers. the first rising edge occurs in the middle of the first data bit (with delay). the spi transmits data one - half cycle ahead of the rising edge of clock signal and receives data on the ris ing edge of clock signal. in case of multi byte transmission, the cs line must be pulsed high between each data word transfer. 0b 1b the clock signal is stopped to high inactive level between transfers. the first falling edge occurs in the middle of the f irst data bit (with delay). the spi transmits data one - half cycle ahead of the falling edge of clock signal and receives data on the falling edge of clock signal. in case of multi byte transmission, the cs line must be pulsed high between each data word tr ansfer. 1b 0b the clock signal is stopped to low inactive level between transfers. the first rising edge occurs at the start of the first data bit (no delay). the spi transmits data on the rising edge of clock signal and receives data on the failing edge of clock signal. 1b 1b the clock signal is stopped to high inactive level between transfers. the first falling edge occurs at the start of the first data bit (no delay). the spi transmits data on the falling edge of clock signal and receives data on the r ising edge of clock signal. 3.8.2.2 procedure for enabling spi the spi initialization procedure is the following (assuming clocks already enabled): 1. clear the sse bit in the cr1 register. this step is not required after a hardware or softwa re reset of the bluenrg1. 2. empty the receive fifo. this step is not required after a hardware or software reset of the device bluenrg1. 3. program io_mode to route spi port signals on those gpios. see section gpio operating modes. 4. program the spi clock prescal er register (cpsr), then program the configuration registers cr0 and cr1. 5. the transmit fifo can optionally be filled before enabling the spi. 6. set the sse bit to enable spi operation.
bluenrg - 1 functional details docid028866 rev 1 51 / 173 the transmit fifo and the receive fifo are not cleared when the sse bi t is cleared. 3.8.2.3 spi bit rate generation the spi bitrate is derived by dividing down the peripheral clock (clk) by an even prescaler value cpsdvsr from 2 to 254, the clock is further divided by a value from 1 to 256, which is 1+scr. t he spi frequency clock duty cycle is always 0.5. 3.8.2.4 spi data endianness all transfers can be sent and received with configurable endianness according the setting of the (t/r)endn bit in the cr1 registers the cases "00b" and "11b" of te ndn and rendn are implemented for data frame size from 4 - to 32 - bit. the cases "01b" and "10b" of tendn and rendn are implemented only for the following data frame sizes: 16 - bit, 24 - bit and 32 - bit. transmit data endianness: tendn in cr1: table 46: spi tx e ndianness tendn endianness 00b the element is transmitted msbyte - first and msbit - first. 01b the element is transmitted lsbyte - first and msbit - first. 10b the element is transmitted msbyte - first and lsbit - first. 11b the element is transmitted lsbyte - firs t and lsbit - first. table 47: spi rx endianness rendn endianness 00b the element is received msbyte - first and msbit - first. 01b the element is received lsbyte - first and msbit - first. 10b the element is received msbyte - first and lsbit - first. 11b the elem ent is received lsbyte - first and lsbit - first. 3.8.2.5 spi interrupts there are six individual maskable interrupt sources generated by the spi (single interrupt signal that drives the nvic): ? receive interrupt ? transmit interrupt ? timeout int errupt ? receive overrun interrupt ? transmit underrun interrupt ? transmit empty interrupt the user can enable or disable the individual interrupt sources by changing the mask bits in the imsc register. setting the appropriate mask bit to 1b enables the interru pt. the status of the individual interrupt sources can be read from the ris register (raw interrupt status) or from the mis register (masked interrupt status).
functional details bluenrg - 1 52 / 173 docid028866 rev 1 3.8.2.6 receive interrupt the receive interrupt is asserted when the number of da ta in receive fifo reaches the programmed trigger watermark level. the receive interrupt is cleared by reading data from the receive fifo until there are less data than the programmed watermark level. 3.8.2.7 transmit interrupt the transmit interrupt is asserted when the number of data in the transmit fifo is less than or equal to the programmed watermark level. it is cleared by performing writes to the transmit fifo until it holds more elements than the programmed watermark level. the transm itter interrupt is not qualified with the spi enable bit, which allows operation in one of two ways: ? data can be written to the transmit fifo prior to enabling the spi and the interrupts. ? or the spi and the interrupts can be enabled so that data can be wr itten to the transmit fifo by an interrupt service routine. 3.8.2.8 timeout interrupt the receive timeout interrupt is asserted when the receive fifo is not empty, and no further data is received over a 32 - bit period of the serial clock. thi s mechanism ensures that the user is aware that data is still present in the receive fifo and requires servicing. the receive timeout interrupt is cleared either when the fifo becomes empty through reading all the data, or if new data is received, or when a 1b is written to the corresponding bit of the icr register. 3.8.2.9 receive overrun interrupt the receive overrun interrupt is asserted when the receive fifo is already full and an additional data frame is received, causing an overrun of t he fifo. data is overwritten in the receive shift register, but not in the fifo. the interrupt is cleared when a 1b is written to the corresponding bit of the icr register. this interrupt can never occur if hardware flow control is enabled in the cr1 regis ter. 3.8.2.10 transmit underrun interrupt the transmit underrun interrupt is asserted when the transmit fifo is already empty and an additional frame is transmitted, causing an underrun of the fifo. data is over - read in the transmit shift reg ister. this interrupt is cleared when a 1b is written to the corresponding bit of the icr register. 3.8.2.11 transmit empty interrupt the transmit interrupt is asserted when the transmit fifo is empty. it is cleared by performing writes to th e transmit fifo. 3.8.2.12 spi master communication mode the spim register field selects the spi transmission mode, these modes are applicable only for spi master mode: ? full duplex mode (spim = 00b): the master transmits the data available in the txfifo and receives the data from the slave. ? transmit mode (spim = 01b): when the data is available in tx fifo, the spi_tx line is run, and no data is written in rx fifo ? receive mode (spim = 10b): the sequence of receive mode is:when the receive mode i s selected we have two cases:
bluenrg - 1 functional details docid028866 rev 1 53 / 173 a. the software sets the mode to receive (spim = 10) and writes the dummy character value to the chn register. b. the software writes the value number of frames to receive from the slave in the rxfrm register. a. if the txfifo is emp ty, the master receives data from the slave, transmitting the character from the chn register in each frame received. the rxfrm register is decremented by one at each transmission/reception. the interface runs until the rxfrm value is dummy and the written number of frames in rxfrm is received. b. if the txfifo is not empty, the master first transmits the data available in the txfifo and receives the data from the slave (like the full duplex mode). the rxfrm register is not decremented. when all the data avail able in txfifo are transmitted, the txfifo becomes empty (case a), then the dummy character from the chn register are transmitted for each frame received. the rxfrm register is decremented for each transaction. when the value in this register is zero and t he written number of frames in rxfrm is received, the interface does not run anymore. the user has to write the rxfrm (with value greater than zero) by software to reactivate the interface. in all cases, the rxfrm is decremented by one only if the txfif o is empty. the rfrm is decremented before the data is sent. if the software fills the txfifo while the spi is transmitting the dummy character, then the words of txfifo should be ignored and we should not send them in this mode, only the dummy - chara cter are transmitted. ? combined mode (spim = 11b): the sequence of combined mode is: a. the software sets the mode to combined mode: (spim=11). b. the software writes to the wdtxf register the "number of frames to be received by the slave (a value greater than zero) from txfifo master". if the number of words written in the wdtxf register are sent (wdtxf is equal to zero) but the rxfrm register is not equal to zero, the master transmits the dummy character (defined in chm register) and receives the slave data, d ecrementing the rxfrm register by one. once the rxfrm register is equal to zero and all the data written in rxfrm are sent, the interface is stopped. when the rxfrm register is zero and wdtxf is not equal to zero and the txfifo of the master and of slave a re not empty, the master transmits the data from txfifo and receives the data from the slave. before the data is sent from txfifo, the wdtxf is decremented by one. when the wdtxf register is zero and all the numbers written in this register are sent, the i nterface is stopped. the interface is stopped when: ? wdtxf and rxfrm registers are equal to zero. ? wdtxf register is not equal to zero and txfifo is empty. ? rxfrm register is not equal to zero, the wdtxf register is zero and txfifo is not empty. for each data transmission (txfifo data or chn register data), the data slave is received. wdtxf is decremented by one only at each data transmission from txfifo. the decrementing is done before the words are sent out.
functional details bluenrg - 1 54 / 173 docid028866 rev 1 rxfrm is decremented by one only at each dummy cha racter transmission from the chn register. the decrementing is done before the words are sent out. when we start decrementing one of the registers (rxfrm or wdtxf), we must decrement until we reach zero and we send the last words before starting the decrem ent of other registers (rxfrm or wdtxf). switching between these different modes when spi is enabled is possible. if the transmission mode is deselected for another mode during a frame transmission, the new mode will become active at the start of the next word. 3.8.3 spi registers spi peripheral base address (spi_base_addr) 0x40400000. table 48: spi registers address offset name rw reset description 0x00 cr0 rw 0x1c000000 control register 0. refer to the detailed description below. 0x04 cr1 rw 0x00000000 control register 1. refer to the detailed description below. 0x08 dr rw 0x00000000 data register. refer to the detailed description below. 0x0c sr r 0x00000003 status register. refer to the detailed description below. 0x10 cpsr rw 0x00 000000 clock prescale register. refer to the detailed description below. 0x14 imsc rw 0x00000000 interrupt mask set or clear register. refer to the detailed description below. 0x18 ris r 0x00000000 raw interrupt status register. refer to the detailed des cription below. 0x1c mis r 0x00000000 masked interrupt status register. refer to the detailed description below. 0x20 icr w 0x00000000 interrupt clear register. refer to the detailed description below. 0x24 dmacr rw 0x00000000 spi dma control register. refer to the detailed description below. 0x28 rxfrm rw 0x00000000 spi receive frame register. indicates the number of frames to receive from the slave. 0x2c chn rw 0x00000000 dummy character register 0x30 wdtxf rw 0x00000000 spi transmit fifo receive fr ame number. indicates the number of frames to receive from the transmit fifo. 0x80 itcr rw 0x00000000 integration test control register. refer to the detailed description below. 0x8c tdr rw 0x00000000 test data register table 49:
bluenrg - 1 functional details docid028866 rev 1 55 / 173 spi - cr0 regist er description: address offset spi_base_addr+0x00 bit field name reset rw description 4:0 dss 0x0 rw data size select. (dss+1) defines the number of bits: 0x00: reserved. 0x01: reserved. 0x02: reserved. 0x03: 4 - bit data. 0x04: 5 - bit data. ... 0x1f: 32 - bit data. 5 reserved 0x0 r reserved 6 spo 0x0 rw clock polarity. 0: steady state of clock polarity is low. 1: steady state of clock polarity is high. 7 sph 0x0 rw clock phase. 0: steady state of clock phase is low. 1: steady state of clock phase is high. 15:8 scr 0x0 rw serial clock rate. the src value is used to generate the transmit and receive bit rate of the spi. the bit rate is: f_spiclk / (cpsdvr * (1 + scr)), where cpsdvr is an even value from 2 to 254 and scr is a value from 0 to 255. 29:22 reserv ed 0x0 r reserved 24:23 spim 0x0 rw spi master transmission mode. 00b: full duplex mode. 01b: transmit mode. 10b: receive mode. 11b: combined mode. 25 reserved 0x0 r reserved 26 cs1 0x1 rw chip selection for slave one 0: the slave 1 is selected. 1: the slave 1 is not selected. 31:27 reserved 0x3 r reserved table 50: spi - cr1 register description: address offset spi_base_addr+0x04 bit field name reset rw description 0 reserved 0x0 r reserved 1 sse 0x0 rw spi enable. 0: spi disable. 1: spi enable. 2 ms 0x0 rw master or slave mode select. 0: master mode. 1: slave mode.
functional details bluenrg - 1 56 / 173 docid028866 rev 1 bit field name reset rw description 3 sod 0x0 rw slave mode output disable (slave mode only). 0: spi can drive the miso signal in slave mode. 1: spi must not drive the miso signal in slave mode. in multiple slave system, it is possible for a spi master to broadcast a message to all slaves in the system while ensuring only one slave drives data onto the serial output line miso. 5:4 rendn 0x0 rw receive endian format. 00b: the element is received msbyte - first and msbit - fir st. 01b: the element is received lsbyte - first and msbit - first. 10b: the element is received msbyte - first and lsbit - first. 11b: the element is received lsbyte - first and lsbit - first. the cases 00b and 11b are set for data frame size from 4 to 32 bits. the ca ses 01b and 10b are set only for data frame size 16, 24 and 32 bits. 6 reserved 0x0 r reserved 9:7 rxiflsel 0x0 rw receive interrupt fifo level select. this bit field selects the trigger points to receive fifo interrupt: 000b: rx fifo contains 1 element or more. 001b: rx fifo contains 4 elements or more. 010b: rx fifo contains 8 elements or more. others: reserved. 12:10 txiflsel 0x0 rw transmit interrupt fifo level select. this bit field selects the trigger points to transmit fifo interrupt: 000b: tx fif o contains 1 element or more. 001b: tx fifo contains 4 elements or more. 010b: tx fifo contains 8 elements or more. others: reserved. 13 reserved 0x0 r reserved 17:14 mspiwait 0x0 rw motorola spi wait mode. this value is used to insert a wait state betwe en frames. 19:18 tendn 0x0 rw transmit endian format. 00b: the element is transmitted msbyte - first and msbit - first. 01b: the element is transmitted lsbyte - first and msbit - first. 10b: the element is transmitted msbyte - first and lsbit - first. 11b: the elemen t is transmitted lsbyte - first and lsbit - first. the cases 00b and 11b are set for data frame size from 4 to 32 bits. the cases 01b and 10b are set only for data frame size 16, 24 and 32 bits. 20 reserved 0x0 r reserved 21 dataindel 0x0 rw data input delay . 0: no delay is inserted in data input. 1: a delay of 2 clock cycles is inserted in the data input path. 31:22 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 57 / 173 table 51: spi - dr register description: address offset spi_base_addr+0x08 bit field name reset rw description 31:0 data 0x0 rw transmit/receive data: read: rx fifo is read. write: tx fifo is written. data must be right - justified when a data size of less than 32 - bit is programmed. unused bits are ignored by the transmit logic. the receive logic automatically right - justi fies data. table 52: spi - sr register description: address offset spi_base_addr+0x0c bit field name reset rw description 0 tfe 0x1 r transmit fifo empty: 0: tx fifo is not empty. 1: tx fifo is empty. 1 tnf 0x1 r transmit fifo not full: 0: tx fifo is f ull. 1: tx fifo is not full. 2 rne 0x0 r receive fifo not empty: 0: rx fifo is empty. 1: rx fifo is not empty. 3 rff 0x0 r receive fifo full: 0: rx fifo is not full. 1: rx fifo is full. 4 bsy 0x0 r spi busy flag: 0: spi is idle. 1: spi is currently tran smitting and/or receiving a frame or the tx fifo is not empty. 31:5 reserved 0x0 r reserved table 53: spi - cpsr register description: address offset spi_base_addr+0x10 bit field name reset rw description 7:0 cpsdvsr 0x0 rw clock prescaler divisor. it must be an even number from 2 to 254. the value is used to generate the transmit and receive bit rate of the spi. the bit rate is: fsspclk / [cpsdvr x (1+scr)] where scr is a value from 0 to 255, programmed through the ssp_cr0 register. 31:8 reserved 0x0 r reserved
functional d etails bluenrg - 1 58 / 173 docid028866 rev 1 table 54: spi - imsc register description. address offset spi_base_addr+0x14. bit field name reset rw description 0 rorim 0x0 rw receive overrun interrupt mask: 0: rx fifo written to while full condition interrupt is masked (irq disabled). 1: rx fifo written to while full condition interrupt is not masked (irq enabled). 1 rtim 0x0 rw receive timeout interrupt mask: 0: rx fifo not empty or no read prior to the timeout period interrupt is masked (irq disabled). 1: rx fifo not empty or no read prior to the timeout period interrupt is not masked (irq enabled). 2 rxim 0x0 rw receive fifo interrupt mask: 0: receive interrupt is masked (irq disabled). 1: receive interrupt is not masked (irq enabled). 3 txim 0x0 rw transmit fifo interrupt mask: 0: transmit interrupt is masked (irq disabled). 1: transmit interrupt is not masked (irq enabled). 4 turim 0x0 rw transmit underrun interrupt mask: 0: transmit underrun interrupt is masked (irq disabled). 1: transmit underrun interrupt is not masked (irq en abled). 5 teim 0x0 rw transmit fifo empty interrupt mask: 0: tx fifo empty interrupt is masked (irq disabled). 1: tx fifo empty interrupt is not masked (irq enabled). 31:6 reserved 0x0 r reserved table 55: spi - ris register description: address offset spi_base_addr+0x18 bit field name reset rw description 0 rorris 0x0 r receive overrun raw interrupt status 1 rtris 0x0 r receive time out raw interrupt status 2 rxris 0x0 r receive raw interrupt status 3 txris 0x0 r transmit raw interrupt status 4 tu rris 0x0 r transmit underrun raw interrupt status 5 teris 0x0 r transmit fifo empty raw interrupt status 31:6 reserved 0x0 r reserved table 56: spi - mis register description: address offset spi_base_addr+0x1c bit field name reset rw description 0 ror mis 0x0 r receive overrun masked interrupt status: gives the interrupt status after masking of the receive overrun interrupt. 1 rtmis 0x0 r receive time out masked interrupt status: gives the interrupt status after masking of receive timeout interrupt. 2 rxmis 0x0 r receive masked interrupt status: gives the interrupt status after masking of the receive interrupt.
bluenrg - 1 functional details docid028866 rev 1 59 / 173 bit field name reset rw description 3 txmis 0x0 r transmit masked interrupt status: gives the interrupt status after masking of the transmit interrupt. 4 turmis 0x0 r transmit u nderrun masked interrupt status: gives the interrupt status after masking of the transmit underrun interrupt. 5 temis 0x0 r transmit fifo empty masked interrupt status: gives the interrupt status after masking of the transmit fifo empty interrupt. 31:6 r eserved 0x0 r reserved table 57: spi - icr register description: address offset spi_base_addr+0x20 bit field name reset rw description 0 roric 0x0 w receive overrun clear interrupt: writing 1 clears the receive overrun interrupt. 1 rtic 0x0 w receive time out clear interrupt: writing 1 clears the receive timeout interrupt. 2 turic 0x0 w transmit underrun clear interrupt: writing 1 clears the transmit overrun interrupt. 31:3 reserved 0x0 r reserved table 58: spi - dmacr register description: address offset spi_base_addr+0x24 bit field name reset rw description 0 rxdmase 0x0 rw single receive dma request. 0: single transfer dma in receive disable. 1: single transfer dma in receive enable. 1 reserved 0x0 r reserved 2 txdmase 0x0 rw single transmit dma request. 0: single transfer dma in transmit disable. 1: single transfer dma in transmit enable. 31:3 reserved 0x0 r reserved table 59: spi C rxfrm register description: address offset spi_base_addr+0x28 bit field name reset rw description 31:0 rxfr m 0x00000000 rw spi receive frame register. indicates the number of frames to receive from the slave. table 60: spi C chn register description: address offset spi_base_addr+0x2c bit field name reset rw description 31:0 chn 0x00000000 rw dummy character register.
functional details bluenrg - 1 60 / 173 docid028866 rev 1 table 61: spi C wdtxf register description: address offset spi_base_addr + 0x30 bit field name reset rw description 31:0 rxfrm 0x00000000 rw spi transmit fifo receive frame number. indicates the number of frames to receive from the tx fifo. table 62: spi - itcr register description: address offset spi_base_addr+0x80 bit field name reset rw description 0 reserved 0x0 r reserved 1 swapfifo 0x0 rw fifo control mode: 0: fifo normal mode. write in tdr register puts data in tx fifo and read fro m tdr register read data from rx fifo. 1: fifo swapped mode. write in tdr register puts data in rx fifo and read from tdr register read data from tx fifo. the registers swapfifo and tdr allow to clear the tx fifo from unwanted data 31:2 reserved 0x0 r res erved table 63: spi C tdr register description: address offset spi_base_addr+0x8c bit field name reset rw description 31:0 tdr 0x00000000 rw allows reading out data from tx fifo if the swapfifo bitfield is set. the registers swapfifo and tdr allow to cl ear the tx fifo from unwanted data
bluenrg - 1 functional details docid028866 rev 1 61 / 173 3.9 uart 3.9.1 introduction the bluenrg - 1 integrates a universal asynchronous receiver/transmitter that support much of the functionality of the industry - standard 16c650 uart. main features are: ? programmable baud rates up to 2 mbps. ? programmable data frame of 5, 6, 7 or 8 bits of data. ? even, odd, stick or no - parity bit generation and detection. ? programmable 1 or 2 stop bit. ? support of hardware flow control using cts and rts pins. ? sup port of software flow control using programmable xon/xoff characters ? false start bit detection. ? line break generation and detection. ? programmable 8 - bit wide, 64 - deep transmit fifo and 12 - bit wide (8 - bit data and 4 - bit status) , 64 - deep receive fifo. ? suppor t for direct memory access (dma). 3.9.2 functional description the uart performs serial - to - parallel conversion on data asynchronously received from a peripheral device on the uart_rx pin, and parallel - to - serial conversion on data written b y cpu for transmission on the uart_tx pin. the transmit and receive paths are buffered with internal fifo memories allowing up to 64 data byte for transmission, and 64 data byte with 4 - bit status (break, frame, parity, and overrun) for receive. fifos may b e burst - loaded or emptied by the system processor from 1 to 16 words per transfer. 3.9.2.1 data transmission or reception data received or transmitted is stored in two 64 - byte fifos. the receive fifo has an extra four bits per character for the status information: ? error bits 8 to 10 are associated with a particular character: break error, parity error and framing error. ? overrun indicator bit 11 is set when the fifo is full, and the next character is completely received in the shift register. the data in the shift register is overwritten, but it is not written into the fifo. when an empty location is available in the receive fifo, and another character is received, the state of the overrun bit is copied into the received fifo along with the rec eived character. the overrun state is then cleared. table 64: rx fifo errors fifo bit function 11 overrun indicator 10 break error 9 parity error 8 framing error 7:0 received data for transmission, data is written into the transmit fifo. if the uart is enabled, it causes a data frame to start transmitting with the parameters indicated in lcrh_tx. data continues to be transmitted until there is no data left in the transmit fifo. the busy flag in the
functional details bluenrg - 1 62 / 173 docid028866 rev 1 uartfr register is set as soon as data is written to the transmit fifo (that is, the fifo is non - empty) and remains asserted while data is being transmitted. busy is cleared only when the transmit fifo is empty, and the last character has been transmitted from the shift register, including the stop bits. bu sy can be set even though the uart might no longer be enabled. for each sample of data, three readings are taken and the majority value is kept. in the following paragraphs, the middle sampling point is defined, and one sample is taken either side of it. w hen the receiver detect a start bit, the receive counter runs and data is sampled on the 8th cycle of that counter in normal uart mode. the start bit is valid if uart_rx signal is still low on the eighth cycle of baud16, otherwise a false start bit is dete cted and it is ignored. if the start bit is valid, successive data bits are sampled on every 16th cycle of baud16 (that is 1 - bit period later) according to the programmed length of the data characters. the parity bit is then checked if parity mode was enab led. lastly, a valid stop bit is confirmed if uart_rx signal is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo, with any error bits associated with that. the uart character frame is shown in figure 9: "uart character frame" below. figure 9 : uart character frame the fifos can be disabled. in this case, the transmit and receive sides of the uart have 1 - byte holding registers (the bo ttom entry of the fifos). the overrun bit is set when a word has been received, and the previous one was not yet read. in this implem entation, the 1 - byte register. 3.9.2.2 baud rate divisor the baud rate divisor is a 22 - bit number consisting of a 16 - bit integer (brdi) and a 6 - bit fractional part (brdf). the fractional baud rate divider enables the use of any clock to act as uart_clk, while it is still possible to generate all the standard baud rates. the 16 - bit integer is loaded through the uart_ibrd register and the 6 - bit fraction al part is loaded into the uart_fbrd register. the baud rate divisor has the following relationship: when bit ovsfact = 0b: divisor = uartclk/(16 x baud rate) = brdi + brdf. when bit ovsfact = 1b: divisor = uartclk/(8 x baud rate) = brdi + brdf. calculati on of the fractional 6 - bit number (divfrac) is done by taking the fractional part of the required baud rate divisor and multiplying it by 64 (that is, 2n, where n is the width of the uart_fbrd register) and adding 0.5 to account for rounding errors: divfra c = integer(brdf * 64 + 0.5)
bluenrg - 1 functional details docid028866 rev 1 63 / 173 the maximum deviation error using a 6 - bit uart_fbrd register is 1/64 * 100 = 1.56%. this occurs when divfrac = 1, and the error is cumulative over 64 clock ticks. example 1 : calculating the divisor value (with ovsfact = 0b). i f the required baud rate is 460 800 and the uart clock frequency is 16 mhz then: baud rate divisor = (16 x 106) / (16 x 460 800) = 2.170 brdi = 2 and brdf = 0.170 therefore fractional part divfrac = integer(brdf * 64 + 0.5) = 11 generated baud rate div ider = 2 + (11 / 64) = 2.1718 generated baud rate = (16 x 106) / (16 x 2.172) = 460 447 error = (460 800 - 460 405) / 460 800 x 100 = 0.077 % an internal clock enable signal, baudl6, is generated, and is a stream of one uartclk wide pulses with an avera ge frequency of 16 (ovsfact = 0b) or 8 (ovsfact = 1b) times the desired baud rate. this signal is then divided by 16 or 8 to give the transmit clock. a low number in the baud rate divisor gives a short bit period, and a high number in the baud rate divisor gives a long bit period. table 65: "typical baud rates with ovsfact = 0" shows some typical bit rates and their corresponding divisors when ovsfact = 0b, given the uart clock frequency of 16 mhz. table 65: typical baud rat es with ovsfact = 0 required bit rate (bps) programmed divisor generated bit rate (bps) error (%) integer (divint) fraction (divfrac) 921 600 1 (16h0001) 5 (6h05) 927 557 0.646 460 800 2 (16h0002) 11 (6h0b) 460 447 - 0.077 230 400 4 (16h0004) 2 2 (6h16) 230 218 - 0.079 115 200 8 (16h0008) 44 (6h2c) 115 107 - 0.081 57 600 17 (16h0011) 23 (6h17) 57 606 0.010 38 400 26 (16h001a) 3 (6h03) 38 392 - 0.021 28 800 34 (16h0022) 46 (6h2e) 28 802 0.007 19 200 52 (16h0034) 5 (6h05) 19 201 0.0 05 9 600 104 (16h0068) 11 (6h0b) 9 599 - 0.010 2 400 416 (16h01a0) 43 (6h2b) 2 399 - 0.042 1 200 833 (16h04b0) 21 (6h15) 1 200 0 300 3333 (16h0d05) 21 (6h15) 300 0 110 9090 (16h2382) 58 (6h3a) 110 0
functional details bluenrg - 1 64 / 173 docid028866 rev 1 table 66: typical baud rates with ovsf act = 1 required bit rate (bps) programmed divisor generated bit rate (bps) error (%) integer (divint) fraction (divfrac) 1 843 200 1 (16h0001) 5 (6h05) 1 855 115 0.646 921 600 2 (16h0002) 11 (6h0b) 920 895 - 0.076 460 800 4 (16h0004) 22 (6h16 ) 461 436 - 0.079 230 400 8 (16h0008) 44 (6h2c) 230 215 - 0.080 115 200 17 (16h0011) 23 (6h17) 115 212 0.010 57 600 34 (16h0022) 46 (6h2e) 57 605 0.009 38 400 52 (16h0034) 5 (6h05) 38 403 0.008 28800 69 (16h0045) 28 (6h1c) 28 802 0.007 19 2 00 104 (16h0068) 11 (6h0b) 19 199 - 0.005 9 600 208 (16h00d0) 21 (6h15) 9 600 0 2 400 833 (16h0341) 21 (6h15) 2 400 0 1 200 1666 (16h0682) 43 (6h2b) 1 199 - 0.083 300 6666 (16h1a0a) 43 (6h2b) 299 - 0.333 110 18181 (16h4705) 52 (6h34) 110 0 3.9.2.3 hardware flow control the hardware flow controls feature is fully selectable through rtsen and ctsen in uartcr register, and allows to control the serial data flow by using the uart_rts output and uart_cts input signals. figure 10 : hardware flow control between two similar devices
bluenrg - 1 functional details docid028866 rev 1 65 / 173 when the rts flow control is enabled, the uart_rts signal is asserted until the receive fifo is filled up to the programmed watermark level. when the cts flow control is enabled, the transmitter can only transmit data when the uart_cts signal is asserted. table 67: control bits to enable and disable hardware flow control ctsen rtsen function 0b 0b both rts and cts flow control disabled. 0b 1b only rts flow control enabled. 1b 0b only cts flow control enabled. 1b 1b both rts and cts flow control enabled. the rts flow control logic is linked to the programmable receive fifo watermark levels. when rts flow control is enabled, the uart_rts is asserted until the receive fifo is fil led up to the watermark level. when the receive fifo watermark level is reached, the uart_rts signal is de - asserted, indicating that there is no more room to receive any more data. the transmission of data is expected to cease after the current character h as been transmitted. the uart_rts signal is reasserted when data has been read out of the receive fifo so that it is filled to less than the watermark level. if rts flow control is disabled and the uart is still enabled, then data is received until the rec eive fifo is full, or no more data is transmitted to it. if cts flow control is enabled, then the transmitter checks the uart_cts signal before transmitting the next byte. if the uart_cts signal is asserted, it transmits the byte otherwise, transmission do es not occur. the data continues to be transmitted while uart_cts is asserted, and the transmit fifo is not empty. if the transmit fifo is empty and the uart_cts signal is asserted no data is transmitted. if the uart_cts signal is de - asserted and cts flow control is enabled, then the current character transmission is completed before stopping. if cts flow control is disabled and the uart is enabled, then the data continues to be transmitted until the transmit fifo is empty. 3.9.2.4 software flow control software flow control is enabled through register uart_xfcr bit sfen. software receive flow control once the software receive flow control is enabled, the receiver compares the incoming data with the programmed xoff values. different combinati ons of software receive flow control, which can be selected through sfrmod, where only 1 character match is needed or in which 2 xoff characters must be received sequentially. table 68: control bits to enable and program receive software flow control sfsen sfrmod function 0b xxb software flow control disabled. 1b 00b software receive flow control disabled. 1b 01b use xon1, xoff1 for matching. 1b 10b use xon2, xoff2 for matching. 1b 11b use xon1 & xon2, xoff1 & xoff2 for matching. if received characte rs match the programmed xoff values, the transmission will stop as soon as the current character is completely transferred. the interrupt bit xoffris in the raw interrupt register uart_ris is set. if the corresponding interrupt mask bit is set, the
functional details bluenrg - 1 66 / 173 docid028866 rev 1 corresp onding bit in the uart_mis register is set and the uart interrupt pin is asserted. following such a transmission suspension, the receiver will monitor incoming characters for a match with the programmed xon values. the matching strategy is programmable thr ough swrfcprog in register uart_xfcr. once a match is found, the receiver clears the interrupt bit xoffris in the raw interrupt register uart_ris and the xoff interrupt is disabled. the transmission can then resume normally. when the xonany bit in register uart_xfcr is set, any incoming character is accepted as a valid xon condition and the transmission can then resume. the received character is written into the received fifo. if the software flow control is enabled, the received xon/xoff characters are never written into the received fifo. exceptions to this occur when the special character detection feature is enabled (xoff2 is then written into fifo upon a special character match) and when the xon - any bit is set. the received status (parity, frami ng and break error) of xon/xoff characters does not have to be valid for these characters to be accepted as valid matches. when the software transmit flow control is enabled through the sftmod bit field in the uart_xfcr register, the transmitter will aut omatically insert an xoff character if the received fifo has passed the received trigger level (bit field rxiflsel in the uart_ifls register). the rtxdis (remote transmitter disabled) bit in the uart_fr register is set to signal the remote transfer was sto pped. when the receive fifo falls below the trigger level, an xon character is automatically inserted in the transmission stream and the rtxdis bit in the uart_fr register is cleared. table 69: control bits to enable and program transmit software flow cont rol sfsen sftmod function 0b xxb software flow control disabled. 1b 00b software transmit flow control disabled. 1b 01b use xon1, xoff1 for matching. 1b 10b use xon2, xoff2 for matching. 1b 11b use xon1 & xon2, xoff1 & xoff2 for matching. after an xoff character has been transmitted, if the software flow controlled is turned off, a xon character will automatically be inserted in the transmission stream and the bit rtxdis bit in the uart_fr register is cleared. transmission of an xon/xoff charac ter follows the standard transmission protocol as programmed in the transmitter registers (word length, parity and so on). when using the software transmit flow control, there are some cautions to take to manage the interrupt handler. the software must react on rx interrupt (the flag will be raised once the rx fifo contains the rxifsel trigger level. then the interrupt handler must first poll the uart_fr.rtxdis bit until it is set to indicate the xoff byte transmission is over and only then read the rx f ifo content. note that hardware and software flow control cannot be enabled simultaneously.
bluenrg - 1 func tional details docid028866 rev 1 67 / 173 software transmit flow control when the special character detection feature is enabled through the spechar bit in the uart_xfcr register, the software flow contro l is turned off and the receiver compares received characters with the xoff2 value. when a match is found, the interrupt bit xoffris in the raw interrupt register uart_ris is set. if the corresponding interrupt mask bit is set, the uart interrupt pin is as serted. the transmission is not halted. the special character is written into the received fifo. the interrupt bit xoffis will be cleared when the corresponding bit in interrupt clear register is written as 1b. it is assumed that software flow control i s turned off when this feature is used. the received status (i.e. parity, framing and break error) of special characters does not have to be valid for these characters to be accepted as valid matches. 3.9.2.5 uart interrupts there are six individual maskable interrupt sources generated by the uart (single interrupt signal that drives the nvic): ? tx fifo empty interrupt ? xoff/ special character interrupt ? receive interrupt ? transmit interrupt ? timeout interrupt ? error interrupt the user can enabl e or disable the individual interrupt sources by changing the mask bits in the uart_imsc register. setting the appropriate mask bit to 1b enables the interrupt. the status of the individual interrupt sources can be read from the uart_ris register (raw inte rrupt status) or from the uart_mis register (masked interrupt status). 3.9.2.6 tx fifo empty interrupt the tx fifo empty interrupt is asserted whenever the busy status bit goes low to indicate that all data has been transmitted. this busy bi t remains set until the complete byte, including all the stop bits, has been sent from the shift register. so, the new tx fifo empty interrupt will be asserted when the transmit fifo and the transmit shift register are empty. 3.9.2.7 xoff/ special character interr upt the xoff/special character interrupt is asserted whenever an xoff condition is detected by the receiver (incoming data matches with the programmable xoff values), or when a special character detection was performed (incoming data matches with the xoff2 and spechar bit set). 3.9.2.8 receive interrupt the receive interrupt is asserted high when one of the following conditions occurs: ? if the fifos are enabled and the number of characters received reaches the programmed trigger watermark level. the receive interrupt is cleared by reading data from the receive fifo until it becomes less than the programmed watermark level, or by clearing the interrupt by writing a 1b to the corresponding bit in the uart_icr register. ? if t he fifos are disabled (have a depth of one location) and there is a data present in the receiver single location. it is cleared by performing a single read.
functional details bluenrg - 1 68 / 173 docid028866 rev 1 3.9.2.9 transmit interrupt the transmit interrupt is asserted high when one of the f ollowing conditions occurs: ? if the fifos are enabled and the number of characters in the transmit fifo is less than the programmed watermark level. it is cleared by performing writes to the transmit fifo until it holds more characters than the programmed w atermark level, or by clearing the interrupt by software. ? if the fifos are disabled (have a depth of one location) and there is no data present in the transmitter single location. it is cleared by performing a single write to the transmit fifo, or by clear ing the interrupt by software. the transmit fifo service interrupt is based on a transition through a level, rather than on the level itself. when the interrupt and the uart are enabled before any data is written to the transmit fifo, the interrupt is n ot set. the interrupt is only set once written data leaves the single location of the transmit fifo and it becomes empty. when the tx fifo is disabled, the data can be written on the bottom of the fifo during the transmission of a previous data, or in another words, when the holding register is busy. the interrupt is de - asserted when we write the next data on the bottom of the tx fifo. if we write data only on the holding register and the bottom of the tx fifo is empty, the only way to clear the int errupt is by the software. 3.9.2.10 timeout interrupt the receive timeout interrupt is asserted when the receive fifo is not empty, and no further data is received (or no correct start bit of a frame is detected in the rx line) over a progr ammable timeout period. this mechanism ensures that the user is aware that data is still present in the receive fifo and requires servicing. the receive timeout interrupt is cleared either when the fifo becomes empty through reading all the data (or by rea ding the holding register), or when a 1b is written to the corresponding bit of the uart_icr register. 3.9.2.11 error interrupt the error interrupt is asserted when an error occurs in the reception of data by the uart. the interrupt can be ca used by the following error conditions: ? framing ? parity ? break ? overrun. the cause of the interrupt is available by reading the uart_ris or uart_mis registers. the interrupt can be cleared by writing to the relevant bits of the uart_icr register.
bluenrg - 1 functional details docid028866 rev 1 69 / 173 3.9.3 uart regis ters uart peripheral base address (uart_base_addr) 0x40300000. table 70: uart registers address offset name rw reset description 0x00 dr rw 0x00000000 data register. refer to the detailed description below. 0x04 rsr r 0x00000000 re ceive status register. refer to the detailed description below. 0x04 ecr rw 0x00000000 error clear register. a write to this register clears the framing (fe), parity (pe), break (be), and overrun (oe) errors. 0x0c timeout rw 0x000001ff timeout register. refer to the detailed description below. 0x18 fr r 0x00001e90 flag register. refer to the detailed description below. 0x1c lcrh_rx rw 0x00000000 receive line control register. refer to the detailed description below. 0x24 ibrd rw 0x00000000 integer baud rate register. refer to the detailed description below. 0x28 fbrd rw 0x00000000 fractional baud rate register. refer to the detailed description below. 0x2c lcrh_tx rw 0x00000000 transmit line control register. refer to the detailed description below. 0x30 cr rw 0x00040300 control register. refer to the detailed description below. 0x34 ifls rw 0x00000012 interrupt fifo level select register. refer to the detailed description below. 0x38 imsc rw 0x00000000 interrupt mask set/clear register. refer to th e detailed description below. 0x3c ris r 0x00000000 raw interrupt status register. refer to the detailed description below. 0x40 mis r 0x00000000 masked interrupt status register. refer to the detailed description below. 0x44 icr w 0x00000000 interrupt clear register. refer to the detailed description below. 0x48 dmacr rw 0x00000000 dma control register. refer to the detailed description below. 0x50 xfcr rw 0x00000000 xon/xoff control register. refer to the detailed description below. 0x54 xon1 rw 0x0 0000000 register used to store the xon1 character used for software flow control. refer to the detailed description below. 0x58 xon2 rw 0x00000000 register used to store the xon2 character used for software flow control. refer to the detailed description below.
functional details bluenrg - 1 70 / 173 docid028866 rev 1 address offset name rw reset description 0x5c xoff1 rw 0x00000000 register used to store the xoff1 character used for software flow control. refer to the detailed description below. 0x60 xoff2 rw 0x00000000 register used to store the xoff2 character used for software flow control. refer to the detailed description below. table 71: uart - dr register description: address offset uart_base_addr+0x00 bit field name reset rw description 7:0 data 0x0 rw uart data register: receive: read data character. transmit: write data character. 8 fe 0 x0 r frame error. this bit is set to 1 if the received character did not have a valid stop bit. in fifo mode, this error is associated with the character at the top of the fifo. 9 pe 0x0 r parity error. this bit is set to 1 if the parity of the received d ata character does not match the parity selected as defined by bits 2 and 7 of the lcrh_rx register. in fifo mode, this error is associated with the character at the top of the fifo. 10 be 0x0 r break error. this bit is set to 1 if a break condition was d etected, indicating that the received data input was held low for longer than a full - word transmission time (defined as start, data, parity and stop bits). in fifo mode, this error is associated with the character at the top of the fifo. when a break occur s, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to high (marking state), and the next valid start bit is received 11 oe 0x0 r overrun error. this bit is set to 1 if data is received and the receive fifo is already full. this is cleared to 0b once there is an empty space in the fifo and a new character can be written to it. the fifo content remains valid since no further data is written when the fifo is full, only the content of the shift register is overwritten. 31:12 reserved 0x0 r reserved table 72: uart - rsr register description: address offset uart_base_addr+0x04 bit field name reset rw description 0 fe 0x0 r frame error. this bit is set to 1 if the received character did not hav e a valid stop bit (a valid stop bit is 1).this bit is cleared to 0b after a write to ecr. in fifo mode, this error is associated with the character at the top of the fifo. 1 pe 0x0 r parity error. this bit is set to 1 if the parity of the received data c haracter does not match the parity selected as defined by bits 2 and 7 of the lcrh_rx register.this bit is cleared to 0b after a write to ecr. in fifo mode, this error is associated with the character at the top of the fifo.
bluenrg - 1 functional details docid028866 rev 1 71 / 173 bit field name reset rw description 2 be 0x0 r break error. this b it is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full - word transmission time (defined as start, data, parity and stop bits). this bit is cleared to 0b after a write to ecr. in fifo mod e, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to high (marking state), and the next valid start bit is received. 3 oe 0x0 r overrun error. this bit is set to 1 if data is received and the receive fifo is already full. this is cleared to 0 by a write to ecr (data value is not important). the fifo contents remain valid since no further data is writte n when the fifo is full, only the content of the shift register are overwritten. the cpu or dma must now read the data in order to empty the fifo. 31:4 reserved 0x0 r reserved table 73: uart - timeout register description: address offset uart_base_addr+ 0x0c bit field name reset rw description 21:0 period 0x1ff rw timeout period configuration. this bit field contains the timeout period for the uart timeout interrupt assertion. the receive timeout interrupt is asserted when the receive fifo is not empty a nd no further data is received over a programmed timeout period. the duration before the timeout interrupt will assert is calculated by the following formula: timeout_duration = (timeout_period) / (ovsp * baud_rate) or timeout_duration = (timeout_period) * baud_divisor * tuartclk 31:22 reserved 0x0 r reserved table 74: uart - fr register description: address offset uart_base_addr+0x18 bit field name reset rw description 0 cts 0x0 r clear to send. 2:1 reserved 0x0 r reserved 3 busy 0x0 r uart busy. if this bit is set to 1, the uart is busy transmitting data. this bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. however, if the transmit section of the uart is disabled in the middle of a transmis sion, the busy bit gets cleared. this bit is set again once the transmit section is re - enabled to complete the remaining transmission.this bit is set as soon as the transmit fifo becomes nonempty (regardless of whether the uart is enabled or not). 4 rxfe 0x1 r receive fifo empty. if the fifo is disabled (bit fen = 0b), this bit is set when the receive holding register is empty. if the fifo is enabled (fen = 1b), the rxfe bit is set when the receive fifo is empty.
functional details bluenrg - 1 72 / 173 docid028866 rev 1 bit field name reset rw description 5 txff 0x0 r transmit fifo full. if the fi fo is disabled (bit fen = 0b), this bit is set when the transmit holding register is full. if the fifo is enabled (fen = 1b), the txff bit is set when the transmit fifo is full. 6 rxff 0x0 r receive fifo full. if the fifo is disabled (bit fen = 0b), this bit is set when the receive holding register is full. if the fifo is enabled (fen = 1b), the rxff bit is set when the receive fifo is full. 7 txfe 0x1 r transmit fifo empty. if the fifo is disabled (bit fen = 0b), this bit is set when the transmit holding register is empty. if the fifo is enabled (fen = 1b), the txfe bit is set when the transmit fifo is empty. 8 reserved 0x0 r reserved 9 dcts 0x1 r delta clear to send. this bit is set cts changes since the last read of the fr register. 12:10 reserved 0x 7 r reserved 13 rtxdis 0x0 r remote transmitter disabled (software flow control). this bit indicates an xoff character was sent to the remote transmitter to stop it after the received fifo has passed over its trigger limit. this bit is cleared when a xon character is sent to the remote transmitter. 31:14 reserved 0x0 r reserved table 75: uart - lcrh_rx register description: address offset uart_base_addr+0x1c bit field name reset rw description 0 reserved 0x0 r reserved 1 pen_rx 0x0 rw rx parity enable : 0: parity disabled. 1: parity enabled. 2 eps_rx 0x0 rw rx even parity selection, when the parity is enabled. 0: odd parity generation and checking is performed during reception, which check for an odd number of 1s in data and parity bits. 1: even parity generation and checking is performed during reception, which check for an even number of 1s in data and parity bits. 3 stp2_rx 0x0 rw rx two stop bits select. this bit enables the check for two stop bits being received: 0: 1 stop bit received. 1: 2 stop bits received. 4 fen_rx 0x0 rw rx enable fifos. this bit enables/disables the receive rx fifo buffer: 0: rx fifo is disabled (character mode). 1: rx fifo is enabled.
bluenrg - 1 functional details docid028866 rev 1 73 / 173 bit field name reset rw description 6:5 wlen_rx 0x0 rw rx word length. this bit field indicates the number of data bits rece ived in a frame as follows: 00b: 5 bits. 01b: 6 bits. 10b: 7 bits. 11b: 8 bits. 7 sps_rx 0x0 rw rx stick parity select: 0: stick parity is disabled. 1: when pen_rx = 1b (parity enabled) and eps_rx = 1b (even parity), the parity is checked as a 0. when pen _rx = 1b and eps_rx = 0b (odd parity), the parity bit is checked as a 1. 31:8 reserved 0x0 r reserved table 76: uart - ibrd register description: address offset uart_base_addr+0x24 bit field name reset rw description 15:0 divint 0x0 rw baud rate intege r. the baud rate divisor is calculated as follows: when ovsfact = 0b in the cr register: baud rate divisor = (frequency (uartclk)/(16*baud rate)) when ovsfact = 1b in cr register: baud rate divisor = (frequency (uartclk)/(8*baud rate)) where frequency (uar tclk) is the uart reference clock frequency. the baud rate divisor comprises the integer value (divint) and the fractional value (divfrac). the contents of the ibrd and fbrd registers are not updated until transmission or reception of the current character has completed. 31:16 reserved 0x0 r reserved table 77: uart - fbrd register description: address offset uart_base_addr+0x28 bit field name reset rw description 5:0 divfrac 0x0 rw baud rate fraction. baud rate integer. the baud rate divisor is calculat ed as follows: when ovsfact = 0b in the cr register: baud rate divisor = (frequency (uartclk)/(16*baud rate)) when ovsfact = 1b in cr register: baud rate divisor = (frequency (uartclk)/(8*baud rate)) where frequency (uartclk) is the uart reference clock fr equency. the baud rate divisor comprises the integer value (divint) and the fractional value (divfrac). the contents of the ibrd and fbrd registers are not updated until transmission or reception of the current character has completed. 31:6 reserved 0x0 r reserved
functional details bluenrg - 1 74 / 173 docid028866 rev 1 table 78: uart - lcrh_tx register description: address offset uart_base_addr+0x2c bit field name reset rw description 0 brk 0x0 rw send break. this bit allows a continuous low - level to be forced on tx output, after completion of the current character. this bit must be asserted for at least one complete frame transmission time in order to generate a break condition. the transmit fifo contents remain unaffected during a break condition. 0: normal transmission. 1: break condition transmission. 1 pen_tx 0x0 rw tx parity enable: 0: parity disabled. 1: parity enable. 2 eps_tx 0x0 rw tx even parity select. this bit selects the parity generation, when the parity is enabled (pen_tx =1b). this bit has no effect when parity is disabled (pen_tx = 0b). 0 : odd parity generation and checking is performed during transmission, which check for an odd number of 1s in data and parity bits. 1: even parity generation and checking is performed during transmission, which check for an even number of 1s in data and pa rity bits. 3 stp2_tx 0x0 rw tx two stop bits select. this bit enables the check for two stop bits being received: 0: 1 stop bit received. 1: 2 stop bits received. 4 fen_tx 0x0 rw tx enable fifo. this bit enables/disables the transmit tx fifo buffer: 0: t x fifo is disabled (character mode), i.e. the tx fifo becomes a 1 - byte deep holding register. 1: tx fifo is enabled. 6:5 wlen_tx 0x0 rw tx word length. this bit field indicates the number of data bits transmitted in a frame as follows: 00b: 5 bits. 01b: 6 bits. 10b: 7 bits. 11b: 8 bits. 7 sps_tx 0x0 rw tx stick parity check: 0: stick parity disable. 1: when pen_tx = 1b (parity enabled) and eps_tx = 1b (even parity), the parity is transmitted as a 0. when pen_tx = 1b and eps_tx = 0b (odd parity), the parit y bit is transmitted as a 1. 31:8 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 75 / 173 table 79: uart - cr register description: address offset uart_base_addr+0x30 bit field name reset rw description 0 en 0x0 rw uart enable. this bit enables the uart. 0: uart is disabled. 1: uar t is enabled. data transmission and reception can occur. when the uart is disabled in the middle of transmission or reception, it completes the current character before stopping. 2:1 reserved 0x0 r reserved 3 ovsfact 0x0 rw uart oversampling factor.this bit enables the uart oversampling factor. if uartclk is 16 mhz thus max. baud - rate is 1 mbaud when ovsfact = 0b, and 2 mbaud when ovsfact = 1b. 0: uart it is 16 uartclk clock cycles. 1: uart it is 8 uartclk clock cycles. 7:4 reserved 0x0 r reserved 8 txe 0x1 rw transmit enable. 0b: uart tx disabled. 1b: uart tx enabled. 9 rxe 0x1 rw receive enable. 0b: uart rx disabled. 1b: uart rx enabled. 10 reserved 0x0 r reserved 11 rts 0x0 rw request to send. 0: rts is high. 1: rts is low. 13:12 reserved 0x0 r re served 14 rtsen 0x0 rw rts hardware flow control enable. 0b: rts disabled. 1b: rts enabled. data is only requested when there is space in the receive fifo for it to be received. 15 ctsen 0x0 rw cts hardware flow control enable. 0b: cts disabled. 1b: cts enabled. data is only transmitted when the cts is asserted. 19:16 sta_b_duration 0x4 rw start bit duration receiver state. these bits can be used to configure the start bit duration (in clock cycles) to get the bit sampled in the middle of the uart receiv er. these bits can be used only when using high baud rates (ibrd = 1, fbrd >= 0 and ovsfact = 1). below the formula to calculate the start bit duration receiver state: sta_b_duration = integer(fuartclk/(2* baud rate)) - 1 example: when uartclk = 16 mhz and baud rate = 2.0 mbps then sta_b_duration = 4 - 1 = 3. sta_b_duration field should be configured with 4'b0011.
functional d etails bluenrg - 1 76 / 173 docid028866 rev 1 bit field name reset rw description 31:20 reserved 0x0 r reserved table 80: uart - ifls register description: address offset uart_base_addr+0x34 bit field name reset rw descripti on 2:0 txiflsel 0x2 rw transmit interrupt fifo level select. this bit field selects the trigger points for tx fifo interrupt: 000b: interrupt when fifo >= 1/64 empty. 001b: interrupt when fifo >= 1/32 empty. 010b: interrupt when fifo >= 1/16 empty. 011b: interrupt when fifo >= 1/8 empty. 100b: interrupt when fifo >= 1/4 empty. 101b: interrupt when fifo >= 1/2 empty. 110b: interrupt when fifo >= 3/4 empty. 5:3 rxiflsel 0x2 rw receive interrupt fifo level select. this bit field selects the trigger points fo r rx fifo interrupt: 000b: interrupt when fifo >= 1/64 full. 001b: interrupt when fifo >= 1/32 full. 010b: interrupt when fifo >= 1/16 full. 011b: interrupt when fifo >= 1/8 full. 100b: interrupt when fifo >= 1/4 full. 101b: interrupt when fifo >= 1/2 full . 110b: interrupt when fifo >= 3/4 full. 31:6 reserved 0x0 r reserved table 81: uart - imsc register description: address offset uart_base_addr+0x38 bit field name reset rw description 0 reserved 0x0 r reserved 1 ctsmim 0x0 rw clear to send modem inte rrupt mask. on a read, the current mask for the ctsmim interrupt is returned. 0: clears the mask (interrupt is disabled). 1: sets the mask (interrupt is enabled). 3:2 reserved 0x0 r reserved 4 rxim 0x0 rw receive interrupt mask. on a read, the current ma sk for the rxim interrupt is returned. 0: clears the mask (interrupt is disabled). 1: sets the mask (interrupt is enabled). 5 txim 0x0 rw transmit interrupt mask. on a read, the current mask for the txim interrupt is returned. 0: clears the mask (interrup t is disabled). 1: sets the mask (interrupt is enabled). 6 rtim 0x0 rw receive timeout interrupt mask. on a read, the current mask for the rtim interrupt is returned. 0: clears the mask (interrupt is disabled). 1: sets the mask (interrupt is enabled).
bluenrg - 1 functional details docid028866 rev 1 77 / 173 bit field name reset rw description 7 feim 0x0 rw framing error interrupt mask. on a read, the current mask for the feim interrupt is returned. 0: clears the mask (interrupt is disabled). 1: sets the mask (interrupt is enabled). 8 peim 0x0 rw parity error interrupt mask. on a read, the curren t mask for the peim interrupt is returned. 0: clears the mask (interrupt is disabled). 1: sets the mask (interrupt is enabled). 9 beim 0x0 rw break error interrupt mask. on a read, the current mask for the beim interrupt is returned. 0: clears the mask (i nterrupt is disabled). 1: sets the mask (interrupt is enabled). 10 oeim 0x0 rw overrun error interrupt mask. on a read, the current mask for the oeim interrupt is returned. 0: clears the mask (interrupt is disabled). 1: sets the mask (interrupt is enabled ). 11 xoffim 0x0 rw xoff interrupt mask. on a read, the current mask for the xoffim interrupt is returned. 0: clears the mask (interrupt is disabled). 1: sets the mask (interrupt is enabled). 12 txfeim 0x0 rw tx fifo empty interrupt mask. on a read, the current mask for the txfeim interrupt is returned. 0: clears the mask (interrupt is disabled). 1: sets the mask (interrupt is enabled). 31:13 reserved 0x0 r reserved table 82: uart - ris register description: address offset uart_base_addr+0x3c bit field name reset rw description 0 reserved 0x0 r reserved 1 ctsmis 0x0 r clear to send interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 3:2 reserved 0x0 r reserved 4 rxis 0x0 r receive interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 5 txim 0x0 r transmit interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 6 rtis 0x0 r receive timeout interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending.
functional details bluenrg - 1 78 / 173 docid028866 rev 1 bit field name reset rw description 7 f eis 0x0 r framing error interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 8 peis 0x0 r parity error interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 9 beis 0x0 r break error interrupt status. 0 : the interrupt is not pending. 1: the interrupt is pending. 10 oeis 0x0 r overrun error interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 11 xoffis 0x0 r xoff interrupt status. 0: the interrupt is not pending. 1: the interr upt is pending. 12 txfeis 0x0 r tx fifo empty interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 31:13 reserved 0x0 r reserved table 83: uart - mis register description: address offset uart_base_addr+0x40 bit field name res et rw description 0 reserved 0x0 r reserved 1 ctsmmis 0x0 r clear to send masked interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 3:2 reserved 0x0 r reserved 4 rxmis 0x0 r receive masked interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 5 txmis 0x0 r transmit masked interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 6 rtmis 0x0 r receive timeout masked interrupt status. 0: the interrupt is not pending. 1: the int errupt is pending. 7 femis 0x0 r framing error masked interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 8 pemis 0x0 r parity error masked interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending.
bluenrg - 1 functional details docid028866 rev 1 79 / 173 bit field name res et rw description 9 bem is 0x0 r break error masked interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 10 oemis 0x0 r overrun error masked interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 11 xoffmis 0x0 r xoff interrup t masked status. 0: the interrupt is not pending. 1: the interrupt is pending. 12 txfemis 0x0 r tx fifo empty masked interrupt status. 0: the interrupt is not pending. 1: the interrupt is pending. 31:13 reserved 0x0 r reserved table 84: uart - icr regi ster description: address offset uart_base_addr+0x44 bit field name reset rw description 0 reserved 0x0 r reserved 1 ctsmic 0x0 w clear to send modem interrupt clear. 0: no effect. 1: clears the interrupt. 3:2 reserved 0x0 r reserved 4 rxic 0x0 w recei ve interrupt clear. 0: no effect. 1: clears the interrupt. 5 txic 0x0 w transmit interrupt clear. 0: no effect. 1: clears the interrupt. 6 rtic 0x0 w receive timeout interrupt clear. 0: no effect. 1: clears the interrupt. 7 feic 0x0 w framing error inte rrupt clear. 0: no effect. 1: clears the interrupt. 8 peic 0x0 w parity error interrupt clear. 0: no effect. 1: clears the interrupt. 9 beic 0x0 w break error interrupt clear. 0: no effect. 1: clears the interrupt. 10 oeic 0x0 w overrun error interrupt clear. 0: no effect. 1: clears the interrupt.
functional details bluenrg - 1 80 / 173 docid028866 rev 1 bit field name reset rw description 11 xoffic 0x0 w xoff interrupt clear. 0: no effect. 1: clears the interrupt. 12 txfeic 0x0 w tx fifo empty interrupt clear. 0: no effect. 1: clears the interrupt. 31:13 reserved 0x0 r reserved table 85: ua rt - dmacr register description: address offset uart_base_addr+0x48 bit field name reset rw description 0 rxdmae 0x0 rw receive dma enable bit. 0: dma mode is disabled for reception. 1: dma mode is enabled for reception. 1 txdmae 0x0 rw transmit dma enab le bit. 0: dma mode is disabled for transmit. 1: dma mode is enabled for transmit. 2 reserved 0x0 r reserved 3 dmaonerr 0x0 rw dma on error. 0: uart error interrupt status has no impact in receive dma mode. 1: dma receive requests are disabled when the u art error interrupt is asserted. 31:4 reserved 0x0 r reserved table 86: uart - xfcr register description: address offset uart_base_addr+0x50 bit field name reset rw description 0 sfen 0x0 rw software flow control enable. 0: software flow control disabl e. 1: software flow control enable. 2:1 sfrmod 0x0 rw software receive flow control mode: 00b: receive flow control is disabled. 01b: xon1, xoff1 characters are used in receiving software flow control. 10b: xon2, xoff2 characters are used in receiving sof tware flow control. 11b: xon1 and xon2, xoff1 and xoff2 characters are used in receiving software flow control. 4:3 sftmod 0x0 rw software transmit flow control mode: 00b: transmit flow control is disabled. 01b: xon1, xoff1 characters are used in transmit ting software flow control. 10b: xon2, xoff2 characters are used in transmitting software flow control. 11b: xon1 and xon2, xoff1 and xoff2 characters are used in transmitting software flow control.
bluenrg - 1 functional details docid028866 rev 1 81 / 173 bit field name reset rw description 5 xonany 0x0 rw xon - any bit: 0: incoming character must match xon programmed value(s) to be a valid xon. 1: any incoming character is considered as a valid xon. 6 spechar 0x0 rw special character detection bit. 0: special character detection disabled. 1: special character detection enabled. 31:7 reserved 0x0 r reserved table 87: uart - xon1 register description: address offset uart_base_addr+0x54 bit field name reset rw description 7:0 xon1 0x0 rw value of xon1 character used in the software flow control 31:8 reserved 0x0 r reserved table 88: uart - xon2 register description. address offset uart_base_addr+0x58. bit field name reset rw description 7:0 xon2 0x0 rw value of xon2 character used in the software flow control 31:8 reserved 0x0 r reserved table 89: uart - xoff1 register description. address o ffset uart_base_addr+0x5c. bit field name reset rw description 7:0 xoff1 0x0 rw value of xoff1 character used in the software flow control 31:8 reserved 0x0 r reserved table 90: uart - xoff2 register description. address offset uart_base_addr+0x60. bit field name reset rw description 7:0 xoff2 0x0 rw value of xoff2 character used in the software flow control 31:8 reserved 0x0 r reserved
functional details bluenrg - 1 82 / 173 docid028866 rev 1 3.10 i 2 c 3.10.1 introduction the bluenrg - 1 integrates two i 2 c controllers. the i 2 c controller is an interface designed to support the physical and data link layer according to the i 2 c standard revision 3.0 and provides a low - cost interconnection between ics. main features are: ? up to 400 kb/s in fast mode and up to 100 kb/s in standa rd mode. ? operating modes supported are master mode, slave mode, master/slave mode for multi - master system with bus arbitration. ? programmable 7 - bit or 10 - bit addressing (also with combined formats). ? programmable start byte procedure. ? 16 - byte depth rx fifo a nd 16 - byte depth tx fifo. ? spike digital filtering on the sda and scl lines. ? control timing constraint defined by the i 2 c standard. ? support for direct memory access (dma). 3.10.2 functional description two wires, serial data (sda) and serial clock (scl) carry information between the devices connected to the bus. each device has a unique address and can operate as either a transmitter or receiver, depending on the function of the device. a master is the device that initiates a data transfer on the bus and generates the clock signal. any device addressed is considered at that time a slave. the i 2 c bus is a multi - master bus where more than one device is capable of controlling the bus. this means that more than one master could try to initiate a d ata transfer at the same time. the arbitration procedure relies on the wired - and connection of all i 2 c interfaces to the i 2 c bus. if two or more masters try to put information onto the bus, the first to produce a one when the other produces a zero will lose the arbitration. the clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired - and connection to the scl line. generation of clock signals on the i2c bus is always the responsibility of mas ter devices; each master generates its own clock signals when transferring data to the bus. bus clock signals from a master can only be altered when they are stretched by a slow slave device holding down the clock line, or by another master when arbitratio n occurs. two modes: ? standard mode with bit rate up to 100 kb/s ? fast mode with bit rate up to 400 kb/s 3.10.2.1 i2c fifo management the transmit and receive paths are buffered with internal fifo memory enabling up to 16 bytes to be stored in dependently in both transmit and receive modes. the fifos status can be checked using the i2c interrupts. there is a programmable threshold value for each fifo. when the number of entries is greater for the receive fifo or less for the transmit fifo, an in terrupt is set.
bluenrg - 1 functional details docid028866 rev 1 83 / 173 3.10.2.2 i2c clock rate calculation to define the i 2 c clock rate generation there is one register to configure: brcr. the clock rate can be calculated using this formula: where: ? f i2c is the i 2 c peripheral clock, clocked o n the system clock divided by 3. ? brcnt2 is a field of the brcr register. ? foncycle depends on a programmable field of the cr register: ? cr: fon = 00 => filter the clock spike wide = 0 => foncycle = 1 ? cr: fon = 01 => filter the clock spike wide = 1 => fo ncycle = 3 ? cr: fon = 10 => filter the clock spike wide = 2 => foncycle = 4 ? cr: fon = 11 => filter the clock spike wide = 4 => foncycle = 6 the minimum input clock frequency for the i 2 c is: ? 1.4 mhz if the i 2 c is in standard mode at 100 khz. ? 7.2 mhz i f the i 2 c is in fast mode at 400 khz. 3.10.2.3 i2c configuration following a reset, the i 2 c logic is disabled and must be configured when in this state. the control register (cr) and baud rate register (brcr) need to be programmed to configur e the following parameters of the peripheral: ? master or slave. ? 7 - or 10 - bit addressing mode ? speed mode ? clock rate if in slave mode, the scr register has to be programmed with the selected slave address. then, if in master mode, the mcr register is us ed to define the transaction: ? read or write. ? slave addresses (7 - or 10 - bit) to communicate with. ? addressing a 7 - or 10 - bit slave address. ? stop condition, to generate a stop or restart condition at the end of the transaction (for consecutive transactions). ? transaction length for a master write, the data to transmit have to be written to the transmit fifo in the i2c_tfr register. for a master read, when the master transaction is done, data are available in the receive fifo in i2c_rfr.
functional details bluenrg - 1 84 / 173 docid028866 rev 1 3.10.2.4 dma interface the i 2 c controller includes a specific dma interface. the following section describes the signals interface, data flow and programming model for the rx and the tx paths. the dma interfaces are separated for each path and two dma request channels shall be used for a device. in rx mode, a dma transfer based on a single descriptor shall be used and the dma rx channel must be programmed for a peripheral - to - memory transfer where the flow controller is the dma. each descriptor is related to a s ingle i 2 c transaction (master read or write - to - slave operation) and no linked list item should be used. the transfer length shall be programmed on the dma and the termination of the frame transfer is notified by the assertion of the related interrupt i2c_r isr:std or i2c_risr:mtd bits. in case of read - from - slave operation, on the dma (master device) the transfer length shall be programmed according to the i2c_mcr:length register field. in case of write - to - slave operation, on the dma (slave device) the maximu m length (not the real length because it is unknown) shall be programmed. in tx mode, a dma transfer based on a single descriptor shall be used and the dma tx channel must be programmed for a memory - to - peripheral transfer where the flow controller is the d ma. each descriptor is related to a single i 2 c transaction (master write or read - from - slave operation) and no linked list item should be used. the transfer length shall be programmed on the dma and the termination of the frame transfer is notified by the a ssertion of the related interrupt i2c_risr:std or i2c_risr:mtd bits. in case of write - to - slave operation, on the dma (master device) the transfer length shall be programmed according to the i2c_mcr:length register field. in case of read - from - slave operatio n, on the dma (slave device) the maximum length (not the real length because it is unknown) shall be programmed. 3.10.3 i 2 c registers i2c2 peripheral base address (i2c2_base_addr) 0x40a00000 i2c1 peripheral base address (i2c1_base_addr) 0x4 0b00000 table 91: i2cx registers address offset name rw reset description 0x00 cr rw 0x00000000 i 2 c control register. refer to the detailed description below. 0x04 scr rw 0x000f0055 i 2 c slave control register. refer to the detailed description below. 0x 0c mcr rw 0x00000000 i 2 c master control register. refer to the detailed description below. 0x10 tfr rw 0x00000000 i 2 c transmit fifo register. refer to the detailed description below. 0x14 sr r 0x00000000 i 2 c status register. refer to the detailed descrip tion below. 0x18 rfr r 0x00000000 i 2 c receive fifo register. refer to the detailed description below. 0x1c tftr rw 0x00000000 i 2 c transmit fifo threshold register. refer to the detailed description below. 0x20 rftr rw 0x00000000 i 2 c receive fifo thresho ld register. refer to the detailed description below.
bluenrg - 1 func tional details docid028866 rev 1 85 / 173 address offset name rw reset description 0x24 dmar rw 0x00000000 i 2 c dma register. refer to the detailed description below. 0x28 brcr rw 0x00000008 i 2 c baud - rate counter register. refer to the detailed description below. 0x2c imscr rw 0x000 00000 i 2 c interrupt mask set/clear register. refer to the detailed description below. 0x30 risr r 0x00000013 i 2 c raw interrupt status register. refer to the detailed description below. 0x34 misr r 0x00000000 i 2 c masked interrupt status register. refer to the detailed description below. 0x38 icr rw 0x00000000 i 2 c interrupt clear register. refer to the detailed description below. 0x4c thddat rw 0x00000014 i 2 c hold time data. refer to the detailed description below. 0x50 thdsta_fst_std rw 0x003f00e2 i 2 c h old time start condition f/s. refer to the detailed description below. 0x54 reserved rw 0x00000019 reserved 0x58 tsusta_fst_std rw 0x001d00e2 i 2 c setup time start condition f/s. refer to the detailed description below. table 92: i 2 c - cr register descr iption: address offset i2cx_base_addr+0x00 bit field name reset rw description 0 pe 0x0 rw i 2 c enable disable: 0: i 2 c disable. 1: i 2 c enable. this bit when deasserted works as software reset for i 2 c peripheral. 2:1 om 0x0 rw select the operating mode: 00 b: slave mode. the peripheral can only respond (transmit/receive) when addressed by a master device 01b: master mode. the peripheral works in a multi - master system where itself cannot be addressed by another master device. it can only initiate a new transf er as master device. 10b: master/slave mode. the peripheral works in a multi - master system where itself can be addressed by another master device, besides to initiate a transfer as master device. 3 sam 0x0 rw slave addressing mode. sam defines the slave a ddressing mode when the peripheral works in slave or master/slave mode. the received address is compared with the content of the register scr. 0: 7 - bit addressing mode. 1: 10 - bit addressing mode.
functional details bluenrg - 1 86 / 173 docid028866 rev 1 bit field name reset rw description 5:4 sm 0x0 rw speed mode. sm defines the speed mode related to the serial bit rate: 0: standard mode (up to 100 k/s). 1: fast mode (up to 400 k/s). 6 sgcm 0x0 rw slave general call mode defines the operating mode of the slave controller when a general call is received. this setting does not affect the hardware ge neral call that is always managed in transparent mode. 0: transparent mode, the slave receiver recognizes the general call but any action is taken by the hardware after the decoding of the message included in the rx fifo. 1: direct mode, the slave receiver recognizes the general call and executes directly (without software intervention) the related actions. only the status code word is stored in the i2c_sr register for notification to the application. 7 ftx 0x0 rw ftx flushes the transmit circuitry (fifo, fsm). the configuration of the i 2 c node (register setting) is not affected by the flushing operation. the flushing operation is performed on modules working on different clock domains (system and i 2 c clocks) and needs several system clock cycles before bei ng completed. upon completion, the i 2 c node (internal logic) clears this bit. the application must not access the tx fifo during the flushing operation and should poll on this bit waiting for completion. 0: flush operation is completed (i2c controller clea rs the bit). 1: flush operation is started and in progress (set by application). 8 frx 0x0 rw frx flushes the receive circuitry (fifo, fsm).the configuration of the i 2 c node (register setting) is not affected by the flushing operation. the flushing operat ion is performed on modules working on different clock domains (system and i 2 c clocks) and needs several system clock cycles before to be completed. upon completion, the i 2 c node (internal logic) clears this bit. the application must not access the rx fifo during the flushing operation and should poll on this bit waiting for the completion. 0: flush operation is completed (i2c controller clears the bit). 1: flush operation is started and in progress (set by application). 9 dma_tx_en 0x0 rw enables the dma tx interface. 0: idle state, the dma tx interface is disabled. 1: run state, the dma tx interface is enabled. on the completion of the dma transfer, the dma tx interface is automatically turned off clearing this bit when the end of transfer signal coming f rom the dma is raised. dma_tx_en and dma_rx_en must not enabled at the same time.
bluenrg - 1 functional details docid028866 rev 1 87 / 173 bit field name reset rw description 10 dma_rx_en 0x0 rw enables the dma rx interface. 0: idle state, the dma rx interface is disabled. 1: run state, the dma rx interface is enabled. on the completion of the dm a transfer, the dma rx interface is automatically turned off clearing this bit when the end of transfer signal coming from the dma is raised. dma_tx_en and dma_rx_en must not enabled at the same time. 14:12 reserved 0x0 r reserved 14:13 fon 0x0 rw filter ing on sets the digital filters on the sda, scl line, according to the i 2 c bus requirements, when standard open - drain pads are used: 00b: no digital filters are inserted. 01b: digital filters (filter 1 ck wide spikes) are inserted. 10b: digital filters (fi lter 2 ck wide spikes) are inserted. 11b: digital filters (filter 4 ck wide spikes) are inserted. 15 fs_1 0x0 rw force stop enable bit. when set to 1b, the stop condition is generated. 0: force stop disabled. 1: enable force stop. 31:16 reserved 0x0 r re served table 93: i 2 c - scr register description: address offset i2cx_base_addr+0x04 bit field name reset rw description 6:0 sa7 0x55 rw slave address 7 - bit. sa7 includes the slave address 7 - bit or the lsb bits of the slave address 10 - bit 9:7 esa10 0x0 rw extended slave address 10 - bit. esa10 includes the extension (msb bits) to the sa7 register field in case of slave addressing mode set to 10 - bit 21:15 reserved 0x0 r reserved 31:16 slsu 0xf rw slave data setup time. slsu defines the data setup time aft er scl clock stretching in terms of i2c_clk cycles. data setup time is actually equal to slsu - 1 clock cycles. the typical values for i2c_clk of 16 mhz are slsu = 5 in standard mode and slsu = 3 in fast modes. table 94: i2c2 - mcr register description: ad dress offset i2cx_base_addr+0x0c bit field name reset rw description 0 op 0x0 rw operation 0: indicates a master write operation. 1: indicates a master read operation. 7:1 a7 0x0 rw address. includes the 7 - bit address or the lsb bits of the10 - bit address used to initiate the current transaction 10:8 ea10 0x0 rw extended address. includes the extension (msb bits) of the field a7 used to initiate the current transaction
functional details bluenrg - 1 88 / 173 docid028866 rev 1 bit field name reset rw description 11 sb 0x0 rw start byte: 0: the start byte procedure is not applied to the current tra nsaction. 1: the start byte procedure is prefixed to the current transaction. 13:12 am 0x0 rw address type: 00b: the transaction is initiated by a general call command. in this case the fields op, a7, ea10 are "don't care". 01b: the transaction is initiat ed by the 7 - bit address included in the a7 field. 10b: the transaction is initiated by the 10 - bit address included in the ea10 and a7 fields. 14 p 0x0 rw stop condition: 0: the current transaction is not terminated by a stop condition. a repeated start co ndition is generated on the next operation which is required to avoid to stall the i 2 c line. 1: the current transaction is terminated by a stop condition. 25:15 length 0x0 rw transaction length. defines the length, in terms of the number of bytes to be tr ansmitted (mw) or received (mr). in case of write operation, the payload is stored in the tx fifo. a transaction can be larger than the tx fifo size. in case of read operation the length refers to the number of bytes to be received before generating a not - acknowledge response. a transaction can be larger than the rx fifo size. the i 2 c clock line is stretched low until the data in rx fifo are consumed. 31:26 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 89 / 173 table 95: i2c - tfr register description: address offset i2cx_base_addr+ 0x10 bit field name reset rw description 7:0 tdata 0x0 rw transmission data. tdata contains the payload related to a master write or read - from - slave operation to be written in the tx fifo. tdata(0) is the first lsb bit transmitted over the i 2 c line. in ca se of master write operation, the tx fifo shall be preloaded otherwise the i 2 c controller cannot start the operation until data are available. in case of read - from - slave operation, when the slave is addressed, the interrupt risr:rfsr bit is asserted and th e cpu shall download the data in the fifo. if the fifo is empty and the i 2 c master is still requiring data, a new request (risr:rfse interrupt bit) is asserted to require additional data to the cpu. the slave controller stretches the i 2 c clock line when no data are available for transmission. since the tx fifo could contain some pending data related to the previous transfer (the transfer length may be unknown to the slave controller), the tx fifo is self - flushed before asserting the i2c_risr:rfsr bit. upon completion of the read - from - slave operation the interrupt bit i2c_risr:std is asserted and the related status of the operation is stored in the i2c_sr register. in cpu mode, the fifo management shall be based on the assertion of the interrupt bit risr:txfn e, related to the nearly - empty threshold. in dma mode, the single/burst requests are automatically executed based on the number of entries available in the tx fifo and the related destination burst size programmed in the i2c_dmar:dbsize_tx register field. the dma requests are terminated at the end of the i 2 c read operation (notacknowledge received by the master) by a dummy last single/burst request. 31:8 reserved 0x0 r reserved table 96: i2c - sr register description: address offset i2cx_base_addr+0x14 b it field name reset rw description 1:0 op 0x0 r operation: 00b: mw: master write operation. 01b: mr: master read operation. 10b: wts: write - to - slave operation. 11b: rfs: read - from - slave operation. 3:2 status 0x0 r controller status. valid for the operati ons mw, mr, wts rfs: 00b: nop: no operation is in progress. 01b: on_going: an operation is ongoing. 10b: ok: the operation (op field) has been completed successfully. 11b: abort: the operation (op field) has been aborted due to the occurrence of the event described in the cause field.
functional details bluenrg - 1 90 / 173 docid028866 rev 1 b it field name reset rw description 6:4 cause 0x0 r abort cause. this field is valid only when the status field contains the abort tag. others: reserved. 000b: nack_addr: the master receives a not - acknowledge after the transmission of the address. valid for the operation mw, mr. 001b: nack_data: the master receives a not - acknowledge during the data phase of a mw operation. valid for the operation mw. 011b: arb_lost: the master loses the arbitration during a mw or mr operation. valid for the operation mw, mr. 100 b: berr_start: slave restarts, a start condition occurs while the byte transfer is not terminated. 101b: berr_stop: slave reset, a stop condition while the byte transfer is not terminated. 110b: ovfl: the slave receives a frame related to the wts operation longer than the maximum size = 2047 bytes. in this case the slave device returns a nack to complete the data transfer. valid for wts operation 8:7 type 0x0 r receive type. valid only for the operation wts: 00b: frame: the slave has received a normal fram e. 01b: gcall: the slave has received a general call. if the it i2c_cr:sgcm is set to 1, the general call is directly executed without software intervention and only the control code word is reported in fifo (length =0). 10b: hw_gcall: the slave has receiv ed a hardware general call. 18:9 length 0x0 r transfer length. for an mr, wts operation the length field defines the actual size of the subsequent payload, in terms of number of bytes. for an mw, rfs operation the length field defines the actual number of bytes transferred by the master/slave device. for a wts operation if the transfer length exceeds 2047 bytes, the operation is stopped by the slave returning a nack handshake and the flag ovfl is set. for an rfs operation if the transfer length exceeds 204 7 bytes, the operation continues normally but the length field is reset to 0. 28: 19 reserved 0x0 r reserved 29 dualf 0x0 r dual flag (slave mode): 0: received address matched with slave address (sa7). 1: received address matched with dual slave address (dsa7). cleared by hardware after a stop condition or repeated start condition, bus error or when pe=0. 31:30 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 91 / 173 table 97: i2c - rfr register description: address offset i2cx_base_addr+0x18 bit field name reset rw description 7:0 rdata 0x0 r receive data. rdata contains the received payload, related to a master read or write - to - slave operation, to be read from the rx fifo. the rdata(0) is the first lsb bit received over the i2c line. in case the fifo is full, the i2c controller st retches automatically the i2c clock line until a new entry is available. for a write - to - slave operation, when the slave is addressed, the interrupt i2c_risr:wtsr bit is asserted for notification to the cpu. in cpu mode the fifo management shall be based on the assertion of the interrupt bit i2c_risr:rxfnf, related to the nearly - full threshold. in dma mode, the single requests are automatically executed based on the number of entries contained in the rx fifo. 31:8 reserved 0x0 r reserved table 98: i2c - t ftr register description: address offset i2cx_base_addr+0x1c bit field name reset rw description 9:0 thresh_tx 0x0 rw threshold tx, contains the threshold value, in terms of number of bytes, of the tx fifo. when the number of entries of the tx fifo is les s or equal than the threshold value, the interrupt bit i2c_risr:txfne is set in order to request the loading of data to the application. 31:10 reserved 0x0 r reserved table 99: i2c - rftr register description: address offset i2cx_base_addr+0x20 bit fiel d name reset rw description 9:0 thresh_rx 0x0 rw threshold rx, contains the threshold value, in terms of number of bytes, of the rx fifo. when the number of entries of the rx fifo is greater than or equal to the threshold value, the interrupt bit risr:rxf nf is set in order to request the download of received data to the application. the application shall download the received data based on the threshold. (risr:rxfnf). 31:10 reserved 0x0 r reserved table 100: i2c - dmar register description: address offs et i2cx_base_addr+0x24 bit field name reset rw description 7:0 reserved 0x0 r reserved 10:8 dbsize_tx 0x0 rw destination burst size. this register field is valid only if the burst_tx bit is set to '1'. if burst size is smaller than the transaction length , only single request are generated.
functional details bluenrg - 1 92 / 173 docid028866 rev 1 bit field name reset rw description 11 burst_tx 0x0 rw defines the type of dma request generated by the dma tx interface. 0: single request mode. transfers a single data (one byte) in the tx fifo. 1: burst request mode. transfers a programmed burst of da ta according to dbsize_tx field. when the burst mode is programmed, the dma transfer can be completed by one or more single requests as required. 31:12 reserved 0x0 r reserved table 101: i2c - brcr register description: address offset i2cx_base_addr+0x2 8 bit field name reset rw description 15:0 brcnt 0x8 rw baud rate counter. brcnt defines the counter value used to set up the i2c baud rate in standard and fast mode, when the peripheral is operating in master mode. 31:16 reserved 0x0 r reserved table 102: i2c - imscr register description: address offset i2cx_base_addr+0x2c bit field name reset rw description 0 txfem 0x0 rw tx fifo empty mask. txfem enables the interrupt bit txfe: 0: txfe interrupt is disabled. 1: txfe interrupt is enabled. 1 txfnem 0 x0 rw tx fifo nearly empty mask. txfnem enables the interrupt bit txfne: 0: txfne interrupt is disabled. 1: txfne interrupt is enabled. 2 txffm 0x0 rw tx fifo full mask. txffm enables the interrupt bit txff: 0: txff interrupt is disabled. 1: txff interrup t is enabled. 3 txfovrm 0x0 rw tx fifo overrun mask. txovrm enables the interrupt bit txovr: 0: txovr interrupt is disabled. 1: txovr interrupt is enabled. 4 rxfem 0x0 rw rx fifo empty mask. rxfem enables the interrupt bit rxfe: 0: rxfe interrupt is disa bled. 1: rxfe interrupt is enabled. 5 rxfnfm 0x0 rw rx fifo nearly full mask. rxnfm enables the interrupt bit rxnf: 0: rxnf interrupt is disabled. 1: rxnf interrupt is enabled 6 rxffm 0x0 rw rx fifo full mask. rxffm enables the interrupt bit rxff: 0: rxf f interrupt is disabled. 1: rxff interrupt is enabled. 15:7 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 93 / 173 bit field name reset rw description 16 rfsrm 0x0 rw read - from - slave request mask. rfsrm enables the interrupt bit rfsr: 0: rfsr interrupt is disabled. 1: rfsr interrupt is enabled. 17 rfsem 0x0 rw read - fro m - slave empty mask. rfsem enables the interrupt bit rfse: 0: rfse interrupt is disabled. 1: rfse interrupt is enabled. 18 wtsrm 0x0 rw write - to - slave request mask. wtsrm enables the interrupt bit wtsr: 0: wtsr interrupt is disabled. 1: wtsr interrupt is e nabled. 19 mtdm 0x0 rw master transaction done mask. mtdm enables the interrupt bit mtd: 0: mtd interrupt is disabled. 1: mtd interrupt is enabled. 20 stdm 0x0 rw slave transaction done mask. stdm enables the interrupt bit std: 0: stdm interrupt is disab led. 1: stdm interrupt is enabled. 23:21 reserved 0x0 r reserved 24 malm 0x0 rw master arbitration lost mask. malm enables the interrupt bit mal: 0: mal interrupt is disabled. 1: mal interrupt is enabled. 25 berrm 0x0 rw bus error mask. berrm enables th e interrupt bit berr: 0: berr interrupt is disabled. 1: berr interrupt is enabled. 27:26 reserved 0x0 r reserved 28 mtdwsm 0x0 rw master transaction done without stop mask. mtdwsm enables the interrupt bit mtdws: 0: mtdws interrupt is disabled. 1: mtdws interrupt is enabled. 31:29 reserved 0x0 r reserved
functional d etails bluenrg - 1 94 / 173 docid028866 rev 1 table 103: i2c - risr register description: address offset i2cx_base_addr+0x30. bit field name reset rw description 0 txfe 0x1 r tx fifo empty. txfe is set when tx fifo is empty. this bit is self - cl eared by writing in tx fifo. 0: tx fifo is not empty. 1: tx fifo is empty. 1 txfne 0x1 r tx fifo nearly empty. txfne is set when the number of entries in tx fifo is less than or equal to the threshold value programmed in the i2c_tftr:threshold_tx register . it is self - cleared when the threshold level is over the programmed threshold. 0: number of entries in tx fifo greater than the tftr:threshold_tx register. 1: number of entries in tx fifo less than or equal to the tftr:threshold_tx register. 2 txff 0x0 r tx fifo full. txff is set when a full condition occurs in tx fifo. this bit is self - cleared when the tx fifo is not full: 0: tx fifo is not full. 1: tx fifo is full. 3 txfovr 0x0 r tx fifo overrun. txfovr is set when a write operation in tx fifo is perfo rmed and tx fifo is full. the application must avoid an overflow condition by a proper data flow control. anyway in case of overrun, the application shall flush the transmitter (cr:ftx bit to set) because the tx fifo content is corrupted (at least one word has been lost in fifo). this interrupt is cleared by setting the related bit of the icr register: 0: no overrun condition occurred in tx fifo. 1: overrun condition occurred in tx fifo. 4 rxfe 0x1 r rx fifo empty. rxfe is set when the rx fifo is empty. th is bit is self - cleared when the slave rx fifo is not empty: 0: rx fifo is not empty.. 1: rx fifo is empty.. 5 rxfnf 0x0 r rx fifo nearly full. rxfnf is set when the number of entries in rx fifo is greater than or equal to the threshold value programmed in the rftr:threshold_rx register. its self - cleared when the threshold level is under the programmed threshold: 0: number of entries in the rx fifo less than the rftr:threshold_rx register. 1: number of entries in the rx fifo greater than or equal to the rft r:threshold_rx register. 6 rxff 0x0 r rx fifo full. rxff is set when a full condition occurs in rx fifo. this bit is self - cleared when the data are read from the rx fifo. 0: rx fifo is not full. 1: rx fifo is full. 14:7 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 95 / 173 bit field name reset rw description 15 lbr 0x 0 r length number of bytes received. lbr is set in case of mr or wts and when the number of bytes received is equal to the transaction length programmed in the mcr:length (master mode) or smb_scr:length (slave mode). on the assertion of this interrupt and when the bit cr:frc_strtch is set, the hardware starts clock stretching, the cpu shall download the data byte (command code, byte count, data...) from rx fifo, re - set the expected length of the transaction in smb_scr:length and clear the interrupt. when cl earing this interrupt the hardware continues the transfer. this interrupt is cleared by setting the related bit of the icr register. 0: length number of bytes is not received. 1: length number of bytes is received. 16 rfsr 0x0 r read - from - slave request. r fsr is set when a read - from - slave "slavetransmitter" request is received (i 2 c slave is addressed) from the i 2 c line. on the assertion of this interrupt the tx fifo is flushed (pending data are cleared) and the cpu shall put the data in tx fifo. this bit is self - cleared by writing data in fifo. in case the fifo is empty before the completion of the read operation, the risr:rfse interrupt bit is set.this interrupt is cleared by setting the related bit of the icr register. 0: read - from - slave request has been s erved. 1: read - from - slave request is pending. 17 rfse 0x0 r read - from - slave empty. rfse is set when a read - from - slave operation is in progress and tx fifo is empty. on the assertion of this interrupt, the cpu shall download in tx fifo the data required fo r the slave operation. this bit is self - cleared by writing in tx fifo. at the end of the read - from - slave operation this bit is cleared although the tx fifo is empty. 0: tx fifo is not empty. 1: tx fifo is empty with the read - from - slave operation in progres s. 18 wtsr 0x0 r write - to - slave request. wtsr is set when a write - to - slave operation is received (i2c slave is addressed) from the i2c line. this notification can be used by the application to program the dma descriptor when required. this interrupt is cl eared by setting the related bit of the icr register: 0: no write - to - slave request pending. 1: write - to - slave request is pending.
functional details bluenrg - 1 96 / 173 docid028866 rev 1 bit field name reset rw description 19 mtd 0x0 r master transaction done. mtd is set when a master operation (master write or master read) has been executed afte r a stop condition. the application shall read the related transaction status (sr register), the pending data in the rx fifo (only for a master read operation) and clear this interrupt (transaction acknowledgment). a subsequent master operation can be issu ed (writing the mcr register) after the clearing of this interrupt. a subsequent slave operation will be notified (risr:wtsr and risr:rfsr interrupt bits assertion) after clearing this interrupt, meanwhile the i 2 c clock line will be stretched low. this int errupt is cleared by setting the related bit of the icr register. 0: master transaction acknowledged. 1: master transaction done (ready for acknowledgment). 20 std 0x0 r slave transaction done. std is set when a slave operation (write - to - slave or read - fro m - slave) has been executed. the application shall read the related transaction status (sr register), the pending data in the rx fifo (only for a write - to - slave operation) and clear this interrupt (transaction acknowledgment). a subsequent slave operation w ill be notified (risr:wtsr and risr:rfsr interrupt bits assertion) after clearing this interrupt, meanwhile the i2c clock line will be stretched low. a subsequent master operation can be issued (by writing the mcr register) after clearing this interrupt. t his interrupt is cleared by setting the related bit of the icr register: 0: slave transaction acknowledged. 1: slave transaction done (ready for acknowledgment). 22:21 reserved 0x0 r reserved 23 sal 0x0 r slave arbitration lost. sal is set when the slave loses the arbitration during the data phase. a collision occurs when 2 devices transmit simultaneously 2 opposite values on the serial data line. the device that is pulling up the line, identifies the collision reading a 0 value on the sda_in signal, stop s the transmission, releases the bus and waits for the idle state (stop condition received) on the bus line. the device which transmits the first unique zero wins the bus arbitration. this interrupt is cleared by setting the related bit of the icr register . 0: no slave arbitration lost. 1: slave arbitration lost. 24 mal 0x0 r master arbitration lost. mal is set when the master loses the arbitration. the status code word in the sr contains a specific error tag (cause field) for this error condition. a colli sion occurs when 2 stations transmit simultaneously 2 opposite values on the serial line. the station that is pulling up the line, identifies the collision reading a 0 value on the sda_in signal, stops the transmission, leaves the bus and waits for the idl e state (stop condition received) on the bus line before retrying the same transaction. the station which transmits the first unique zero wins the bus arbitration. this interrupt is cleared by setting the related bit of the icr register. 0: no master arbit ration lost. 1: master arbitration lost.
bluenrg - 1 functional details docid028866 rev 1 97 / 173 bit field name reset rw description 25 berr 0x0 r bus error. berr is set when an unexpected start/stop condition occurs during a transaction. the related actions are different, depending on the type of operation in progress.the status code word in th e sr contains a specific error tag (cause field) for this error condition. this interrupt is cleared by setting the related bit of the icr register. 0: no bus error detection. 1: bus error detection. 27:26 reserved 0x0 r reserved 28 mtdws 0x0 r master tr ansaction done without stop. mtdws is set when a master operation (write or read) has been executed and a stop (mcr:p field) is not programmed. the application shall read the related transaction status (sr register), the pending data in the rx fifo (only f or a master read operation) and clear this interrupt (transaction acknowledgment). a subsequent master operation can be issued (by writing the mcr register) after clearing this interrupt. a subsequent slave operation will be notified (risr:wtsr and risr:rf sr interrupt bits assertion) after clearing this interrupt, meanwhile the i 2 c clock line will be stretched low. this interrupt is cleared by setting the related bit of the icr register: 0: master transaction acknowledged. 1: master transaction done (ready for acknowledgment) and stop is not applied into the i 2 c bus. 31:29 reserved 0x0 r reserved table 104: i2c - misr register description: address offset i2cx_base_addr+0x34 bit field name reset rw description 0 txfemis 0x0 r tx fifo empty masked interrup t status. 0: tx fifo is not empty. 1: tx fifo is empty. 1 txfnemis 0x0 r tx fifo nearly empty masked interrupt status. 0: number of entries in tx fifo greater than the tftr:threshold_tx register. 1: number of entries in tx fifo less than or equal to the t ftr:threshold_tx register. 2 txffmis 0x0 r tx fifo full masked interrupt status. 0: tx fifo is not full. 1: tx fifo is full. 3 txfovrmis 0x0 r tx fifo overrun masked interrupt status. 0: no overrun condition occurred in tx fifo. 1: overrun condition occu rred in tx fifo. 4 rxfemis 0x0 r rx fifo empty masked interrupt status. 0: rx fifo is not empty. 1: rx fifo is empty.
functional details bluenrg - 1 98 / 173 docid028866 rev 1 bit field name reset rw description 5 rxfnfmis 0x0 r rx fifo nearly full masked interrupt status. 0: number of entries in the rx fifo less than the rftr:threshold_rx regist er. 1: number of entries in the rx fifo greater than or equal to the rftr:threshold_rx register. 6 rxffmis 0x0 r rx fifo full masked interrupt status. 0: rx fifo is not full. 1: rx fifo is full. 14:7 reserved 0x0 r reserved 15 lbrmis 0x0 r length number of bytes received masked interrupt status. 0: length number of bytes is not received. 1: length number of bytes is received. 16 rfsrmis 0x0 r read - from - slave request masked interrupt status. 0: read - from - slave request has been served. 1: read - from - slave request is pending. 17 rfsemis 0x0 r read - from - slave empty masked interrupt status. 0: tx fifo is not empty. 1: tx fifo is empty with the read - from - slave operation in progress. 18 wtsrmis 0x0 r write - to - slave request masked interrupt status. 0: no write - to - slave request pending. 1: write - to - slave request is pending. 19 mtdmis 0x0 r master transaction done masked interrupt status. 0: master transaction acknowledged. 1: master transaction done (ready for acknowledgment). 20 stdmis 0x0 r slave transaction done masked interrupt status. 0: slave transaction acknowledged. 1: slave transaction done (ready for acknowledgment). 22:21 reserved 0x0 r reserved 23 salmis 0x0 r slave arbitration lost masked interrupt status. 0: no slave arbitration lost. 1: slave ar bitration lost. 24 malmis 0x0 r master arbitration lost masked interrupt status. 0: no master arbitration lost. 1: master arbitration lost. 25 berrmis 0x0 r bus error masked interrupt status. 0: no bus error detection. 1: bus error detection. 27:26 rese rved 0x0 r reserved 28 mtdwsmis 0x0 r master transaction done without stop masked interrupt status. 0: master transaction acknowledged. 1: master transaction done (ready for acknowledgment) and stop is not applied into the i 2 c bus.
bluenrg - 1 functional details docid028866 rev 1 99 / 173 bit field name reset rw description 29 pecerrmis 0x0 r pec error in reception masked interrupt status. 0: no pec error: receiver returns ack after pec reception (if cr:nack = 0). 1: pec error: receiver returns nack after pec reception (whatever cr:nack). 30 timeoutmis 0x0 r timeout or tlow error masked interrupt status. 0: no timeout error. 1: scl remained low for 25 ms (timeout). 31 reserved 0x0 r reserved table 105: i2c - icr register description: address offset i2cx_base_addr+0x38 bit field name reset rw description 2:0 reserved 0x0 r reserved 3 txfovric 0x0 rw tx fifo overrun interrupt clear. 0: has no effect. 1: clears interrupt pending. 14:4 reserved 0x0 r reserved 15 lbric 0x0 rw length number of bytes received interrupt clear. 0: has no effect. 1: clears interrupt pending. 16 rfsric 0x0 rw read - fro m - slave request interrupt clear. 0: has no effect. 1: clears interrupt pending. 17 rfseic 0x0 rw read - from - slave empty interrupt clear. 0: has no effect. 1: clears interrupt pending. 18 wtsric 0x0 rw write - to - slave request interrupt clear. 0: has no effe ct. 1: clears interrupt pending. 19 mtdic 0x0 rw master transaction done interrupt clear. 0: has no effect. 1: clears interrupt pending. 20 stdic 0x0 rw slave transaction done interrupt clear. 0: has no effect. 1: clears interrupt pending. 22:21 reserve d 0x0 r reserved 23 salic 0x0 rw slave arbitration lost interrupt clear. 0: has no effect. 1: clears interrupt pending. 24 malic 0x0 rw master arbitration lost interrupt clear. 0: has no effect. 1: clears interrupt pending.
functional details bluenrg - 1 100 / 173 docid028866 rev 1 bit field name reset rw description 25 berric 0x0 rw bus error in terrupt clear. 0: has no effect. 1: clears interrupt pending. 27:26 reserved 0x0 r reserved 28 mtdwsic 0x0 rw master transaction done without stop interrupt clear. 0: has no effect. 1: clears interrupt pending. 29 pecerric 0x0 rw pec error in reception interrupt clear. 0: has no effect. 1: clears interrupt pending. 30 timeoutic 0x0 rw timeout or tlow error interrupt clear. 0: has no effect. 1: clears interrupt pending. 31 reserved 0x0 r reserved table 106: i2c - thddat register description: address o ffset i2cx_base_addr+0x4c bit field name reset rw description 8:0 thddat 0x14 rw hold time data value. in master or slave mode, when the i2c controller detects a falling edge in the scl line, the counter, which is loaded by the thddat, is launched. once t he thddat value is reached, the data is transferred. 31:9 reserved 0x0 r reserved table 107: i2c - thdsta_fst_std register description: address offset i2cx_base_addr+0x50 bit field name reset rw description 8:0 thdsta_std 0xe2 rw hold time start condit ion value for standard mode. when the start condition is asserted, the decimeter loads the value of thdsta_std for standard mode, once the thdsta_std value is reached, the scl line asserts low. 22:15 reserved 0x0 r reserved 24:16 thdsta_fst 0x3f rw hold time start condition value for fast mode. when the start condition is asserted, the decimeter loads the value of thdsta_fst for fast mode, once the thdsta_fst value is reached, the scl line assert slow. 31:25 reserved 0x0 r reserved table 108: i2c - tsu sta_fst_std register description: address offset i2cx_base_addr+0x58 bit field name reset rw description 8:0 tsusta_std 0xe2 rw setup time start condition value for standard mode. after a non - stop on the scl line the decimeter loads the value of tsusta_st d according to standard mode. once the counter is expired, the start condition is generated. 22:15 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 101 / 173 bit field name reset rw description 24:16 tsusta_fst 0x1d rw setup time start condition value for fast mode. after a non - stop on the scl line the decimeter loads the v alue of tsusta_fst according to fast mode. once the counter is expired the start condition is generated. 31:25 reserved 0x0 r reserved 3.11 flash controller 3.11.1 flash controller introduction the bluenrg - 1 integrates a flash controller to interface the embedded flash memory. main features are: ? sector erase and mass erase ? 160 kbyte flash memory: 80 pages of 8 rows with 64 words each ? flash programming ? mass read ? enable readout protection ? 32 - bit read access ? 32 - bit write a ccess in single write and 4x32 - bit in burst write (reduce programming time by 2) 3.11.2 flash controller functional description the bluenrg - 1 embeds up to 160 kb (40960 x 32 - bit) of internal flash memory. a flash interface implements instru ction access and data access based on the ahb protocol. it implements the logic necessary to carry out the flash memory operations (program/erase) controlled through the flash registers. writing to flash only allows clearing bits from 1 to 0. this mean s any write from 0 to 1 implies erasing before performing a write. flash memory is composed of 80 pages containing 8 rows of 64 words (80 x 8 x 64 = 40960 words). each word is 32 - bit = 4 bytes long which means 160 kb of flash. the address inside the ad dress register is built as follows: address[13:0] = xadr[9:0] & yadr[5:0] with: ? xadr[9:3] = page address ? xadr[2:0] = row address ? yadr[5:0] = word address (one word = four bytes) one specific address can be written only twice between two erase actions ev en if each writing only clears bits. 3.11.2.1 reading flash memory there are two possible read accesses: ? read one single word: simple read as if ram memory: read the desired flash address and get read data on the bus.
functional details bluenrg - 1 102 / 173 docid028866 rev 1 ? massread command: read the full flash memory and compare with expected content there are two ways of using massread: 1. full flash contains a fixed 32 - bit pattern: indicate the expected pattern (value to be compared with each read value inside flash) in the data register and check the readok flag in the interrupt register once the command is completed. 2. request a massread command without specifying any expected read value and check the lfsrval register once the command is completed. this lfsrval register contains a signature of the memory read, built according to the following polynomial: x32 + x31 + x4 + x3 + x1 + 1 (seed value = 0xffff_ffff). massread sequence: 1. write in the data register the expected value (if massread is used in combination with the readok flag). 2. write the massrea d command (0x55) in the command register. 3. wait for the cmdstart flag in the irqstat register (polling mode or interrupt mode) indicating that the command has been taken into account and is under execution. 4. clear the cmdstart flag by writing cmdstart to 1 in the irqstat register. 5. wait for the cmddone flag in the irqstat register (polling mode or interrupt mode) indicating that the command is completed. 6. check the readok flag (expected high) in the irqstat register or the lfsrval register value to ensure fla sh memory content is the expected result. 7. clear the cmddone flag by writing cmddone to 1 in the irqstat register. 3.11.2.2 erasing flash the flash controller allows erasing one page or the full main flash. erase sequence (erase one page): 1. write the page address to be erased by writing in the address register the following value: a. address[15:9] = xadr[9:3] = page address to erase b. address[8:0] = 9b0 (row and word addresses at zero). 2. write the erase command (0x11) in the command register. 3. wait for the cmdstart flag in the irqstat register (polling mode or interrupt mode) indicating command is taken into account and under execution. 4. clear the cmdstart flag by writing cmdstart to 1 in the irqstat register. 5. wait for the cmddone flag in the irqst at register (polling mode or interrupt mode) indicating that the command is completed. 6. clear the cmddone flag by writing cmddone to 1 in the irqstat register. after this command, the erased page will contain only bits set to 1. masserase sequence (eras e completely main flash): 1. write the masserase command (0x22) in the command register. 2. wait for the cmdstart flag in the irqstat register (polling mode or interrupt mode) indicating that the command has been taken into account and is under execution. 3. clear the cmdstart flag by writing cmdstart to 1 in the irqstat register. 4. wait for the cmddone flag in the irqstat register (polling mode or interrupt mode) indicating that the command is completed. 5. clear the cmddone flag by writing cmddone to 1 in the irqst at register. after this command, the full main flash will contain only bits set to 1.
bluenrg - 1 functional details docid028866 rev 1 103 / 173 3.11.2.3 write function examples the flash controller allows writing one word (write), up to 4 words (burstwrite) or the full main flash memory (with a si ngle fixed word). note: as a write can only program to 0 on bits already set to 1, it is necessary to erase the page and request that the bits be set to 1 (instead of 0) in order to re - write to 0. write sequence: 1. indicate the location to write by filling the address register with the targeted address (page, row and word number) 2. write the value to program in the data register. 3. write the write command (0x33) in the command register. 4. wait for the cmdstart flag in the irqstat register (polling mode or interrupt mode) indicating that the command has been taken into account and is under execution. 5. clear the cmdstart flag by writing cmdstart to 1 in the irqstat register. 6. wait for the cmddone flag in the irqstat register (polling mode or interrupt mode) indicating that the command is completed. 7. clear the cmddone flag by writing cmddone to 1 in the irqstat register. busrtwrite sequence: 1. indicate the location to write by filling the address register with the targeted address of the first data to write (pa ge, row and word number). data0 will be written and address, data1 at address+1 and so on. (write the values to program in the data0 - 3 registers. to write less than four words, write 0xffffffff in the unused data1 - 3 registers.) 2. write the burstwrite command (0xcc) in the command register. 3. wait for the cmdstart flag in the irqstat register (polling mode or interrupt mode) indicating that the command has been taken into account and is under execution. 4. clear the cmdstart flag by writing cmdstart to 1 in the i rqstat register. 5. wait for the cmddone flag in the irqstat register (polling mode or interrupt mode) indicating that the command is completed. 6. clear the cmddone flag by writing cmddone to 1 in the irqstat register. masswrite sequence: 1. write the unique val ue to program in all the main flash memory in the data register. 2. write the masswrite command (0x44) in the command register. 3. wait for the cmdstart flag in the irqstat register (polling mode or interrupt mode) indicating that the command has been taken into account and is under execution. 4. clear the cmdstart flag by writing cmdstart to 1 in the irqstat register. 5. wait for the cmddone flag in the irqstat register (polling mode or interrupt mode), indicating that the command is completed. 6. clear the cmddone fla g by writing cmddone to 1 in the irqstat register. 3.11.2.4 flash readout protection it is possible to protect flash memory from unwanted access while in debug mode, this is normally used to avoid copy or reverse engineering of a deployed a pplication in the market. if the readout protection mechanism is activated, as soon as cortex - m0 is halted, any access to flash memory will return a fixed 0x0 value and generate an ahb error if a debugger tries to read it. note that ram memory debug access es are also disabled by this lock protection.
functional details bluenrg - 1 104 / 173 docid028866 rev 1 enabling readout protection: 1. program a secret 64 bit sequence in the last two word address of the user flash. the secret 64 bit sequence can be anything different from 0xffffffff, 0xffffffff. disable readout pr otection: 1. perform a mass erase of the user flash 3.11.2.5 flash command list the valid command values list for the command register is reported in the table below. table 109: flash commands command name description value erase erase page def ined by register address 0x11 masserase mass erase (flash is complexly erased) 0x22 write program one location (defined by registers data and address) 0x33 masswrite program all locations with the same value (data register value) 0x44 massread read all locations and compare with data register value or produce lfsr signature 0x55 burstwrite burst write operation 0xcc 3.11.2.6 flash interface timing characteristics table 110: flash interface timing description min typ max unit page eras e time 20 21.5 40 ms mass erase time 20 21.5 40 ms program time write 20 21 40 us program time burstwrite 20 11 40 us 3.11.3 flash controller registers flash controller peripheral base address (flash_base_addr) 0x40100000. table 111: flash controller registers address offset name rw reset description 0x00 command rw 0x00000000 commands for the module 0x04 config rw 0x00000000 configure the wrapper 0x08 irqstat rw 0x00000000 flash status interrupt (masked). refer to the detailed desc ription below. 0x0c irqmask rw 0x0000003f mask for interrupts. refer to the detailed description below. 0x10 irqraw rw 0x00000000 status interrupts (unmasked). refer to the detailed description below.
bluenrg - 1 functional details docid028866 rev 1 105 / 173 address offset name rw reset description 0x14 size r 0x00000000 indicates the last usable add ress of the main flash 0x18 address rw 0x00000000 address for programming flash, will auto - increment 0x24 lfsrval r 0xffffffff lfsr register needed for check after mass read command 0x28 timetrim1 rw 0x0b061515 trimming values for flash erase/modify seq uences 0x2c timetrim2 rw 0x0b156506 trimming values for flash erase/modify sequences 0x30 timetrim3 rw 0x00000011 trimming values for flash wake - up sequence 0x40 data0 rw 0xffffffff program cycle data 0x44 data1 rw 0xffffffff program cycle data 0x48 d ata2 rw 0xffffffff program cycle data 0x4c data3 rw 0xffffffff program cycle data table 112: flash C command register description: address offset flash_base_addr+0x00 bit field name reset rw description 31:0 command 0x00000000 rw command for the module . table 113: flash C config register description: address offset flash_base_addr+0x04 bit field name reset rw description 31:0 config 0x00000000 rw configure the wrapper. table 114: flash - irqstat register description: address offset flash_base_addr +0x08 bit field name reset rw description 0 cmddone 0x0 rw command is done. 1: clear the interrupt pending bit. 1 cmdstart 0x0 rw command is started.1: clear the interrupt pending bit. 2 cmderr 0x0 rw command written while busy. 1: clear the interrupt p ending bit. 3 illcmd 0x0 rw illegal command written. 1: clear the interrupt pending bit. 4 readok 0x0 rw mass read was ok. 1: clear the interrupt pending bit. 5 flnready 0x0 rw flash not ready (sleep). 1: clear the interrupt pending bit. 31:6 reserved 0x0 r reserved
functional details bluenrg - 1 106 / 173 docid028866 rev 1 table 115: flash - irqmask register description: address offset flash_base_addr+0x0c bit field name reset rw description 0 cmddone 0x1 rw command is done. 1 cmdstart 0x1 rw command is started. 2 cmderr 0x1 rw command written while bus y 3 illcmd 0x1 rw illegal command written 4 readok 0x1 rw mass read was ok. 5 flnready 0x1 rw flash not ready (sleep). 31:6 reserved 0x0 r reserved table 116: flash - irqraw register description: address offset flash_base_addr+0x10 bit field name res et rw description 0 cmddone 0x0 rw command is done. 1 cmdstart 0x0 rw command is started. 2 cmderr 0x0 rw command written while busy 3 illcmd 0x0 rw illegal command written 4 readok 0x0 rw mass read was ok. 5 flnready 0x0 rw flash not ready (sleep). 31:6 reserved 0x0 r reserved table 117: flash C size register description: address offset flash_base_addr+0x14 bit field name reset rw description 31:0 size 0x00000000 r indicates the last usable address of the flash. table 118: flash C address regis ter description: address offset flash_base_addr+0x18 bit field name reset rw description 31:0 address 0x00000000 rw address for programming flash, will auto - increment. table 119: flash C lfsrval register description: address offset flash_base_addr+0x24 bit field name reset rw description 31:0 lfsrval 0xffffffff r lfsr register needed for check after massread command. table 120: flash C timetrim1 register description: address offset flash_base_addr+0x28 bit field name reset rw description 31:0 timetri m1 0x0b061515 rw trimming values for flash erase/modify sequences.
bluenrg - 1 functional detai ls docid028866 rev 1 107 / 173 table 121: flash C timetrim2 register description: address offset flash_base_addr+0x2c bit field name reset rw description 31:0 timetrim2 0x0b156506 rw trimming values for flash erase/mo dify sequences. table 122: flash C timetrim3 register description: address offset flash_base_addr+0x30 bit field name reset rw description 31:0 timetrim3 0x00000011 rw trimming values for flash wake - up sequence. table 123: flash C data0 register descr iption: address offset flash_base_addr+0x40 bit field name reset rw description 31:0 data0 0xffffffff rw program cycle data. table 124: flash C data1 register description: address offset flash_base_addr+0x44 bit field name reset rw description 31:0 dat a1 0xffffffff rw program cycle data. table 125: flash C data2 register description: address offset flash_base_addr+0x48 bit field name reset rw description 31:0 data2 0xffffffff rw program cycle data. table 126: flash C data3 register description: add ress offset flash_base_addr+0x4c bit field name reset rw description 31:0 data3 0xffffffff rw program cycle data.
functional details bluenrg - 1 108 / 173 docid028866 rev 1 3.12 gpio 3.12.1 introduction the bluenrg - 1 offers 14 gpios (wcsp34 package) or 15 gpios (qfn32 pack age). the programmable i/o pin can be configured for operating as: ? programmable gpios ? peripheral input or output line of standard communication interfaces ? pdm processor data/clock ? 2 pwm sources (pwm0 and pwm1 independently configurable) and 4 pwm output p ins (io2, io3, io4 and io5). ? 5 wakeup sources from standby and sleep mode ? each i/o can generate an interrupt independently to the selected mode. interrupts are generated depending on a level or edge 3.12.2 functional description in the tab le below is reported the gpio configuration table where at each io pin is associated the related functions. table 127: io functional map pin name gpio mode "000" mode serial1 '001" mode serial0 100 101 io0 i/o gpio 0 i uart_cts i/o spi_clk - - io1 i/o gpio 1 o uart_rts i/o spi_cs1 i pdm_data io2 i/o gpio 2 o pwm0 o spi_out o pdm_clk io3 i/o gpio 3 o pwm1 i spi_in o adc_clk io4 i/o gpio 4 i uart_rxd i/o i2c2_clk o pwm0 io5 i/o gp io 5 o uart_txd i/o i2c2_dat o pwm1 io6 i/o gpio 6 o uart_rts i/o i2c2_clk i pdm_data io7 i/o gpio 7 i uart_cts i/o i2c2_dat o pdm_clk io8 i/o gpio 8 o uart_txd i/o spi_clk i pdm_data io9 i/o gpio 9 i swclk i spi_in - - io10 i/o gpio 10 i swdio o spi_ out - - io11 i/o gpio 11 i uart_rxd i/o spi_cs1 - - io12 od gpio 12 i - i/o i2c1_clk a - - io13 od gpio 13 i uart_cts i/o i2c1_dat a - - io14 i/o gpio 14 i/o i2c1_clk i/o spi_clk o adc_data a i2c io12 and io13 need external pull - up
bluenrg - 1 functional details docid028866 rev 1 109 / 173 3.12.2.1 gpio interrupts each io in gpio mode can be used as interrupt source from external signal. the trigger event is both edge and level sensitive according to configuration. all the configuration are reported in table below. table 128: gpio interrupt modes config uration interrupt mode falling edge rising edge both edges low level high level iois 0 0 0 1 1 ioibe 0 0 1 na na ioiev 0 1 na 0 1 the interrupt is enabled by writing 1 in the io_mis register, in the position with same number of the io desired. once the interrupt occurs, it can be cleared by writing 1 in the io_ic register. all the interrupts drive a single interrupt signal of the nvic. 3.12.2.2 gpio characteristics by default all the gpio pins are configured as input with related pull - up or pull - down resistor enabled according to table below. table 129: pin characteristics name type buffer strength pull - up / pull - down availability reset state io0 i/o 2 / 4 ma pull - down input pull - down io1 i/o 2 / 4 ma pull - down input pull - down io2 i/ o 2 / 4 ma pull - down input pull - down io3 i/o 2 / 4 ma pull - down input pull - down io4 i/o 2 / 4 ma pull - down input pull - down io5 i/o 2 / 4 ma pull - down input pull - down io6 i/o 2 / 4 ma pull - down input pull - down dio7 i/o 2 / 4 ma pull - down input pull - dow n io8 i/o 2 / 4 ma pull - down input pull - down io9 i/o 2 / 4 ma pull - up input pull - up io10 i/o 2 / 4 ma pull - up input pull - up io11 i/o 2 / 4 ma pull - up input pull - up io12 i/o 10 ma no pull input io13 i/o 10 ma no pull input io14 i/o 2 / 4 ma pull - do wn input pull - down table 130: io pull values name description name min. typ. max. unit digital input and output when 1.8 v supply. rpd pull - down value 117 202 363 k? rpu pull - up value 135 211 334
functional details bluenrg - 1 110 / 173 docid028866 rev 1 name description name min. typ. max. unit digital input and output when 3.3v supply. rpd p ull - down value 53 84 144 k? rpu pull - up value 57 81 122
bluenrg - 1 functional details docid028866 rev 1 111 / 173 3.12.3 gpio registers gpio peripheral base address (gpio_base_addr) 0x40000000. table 131: gpio registers address offset name rw reset description 0x00 data rw 0x00000000 io0 t o io14 data value. writing to a bit will drive the written value on the corresponding io when it is configured in gpio mode and the output direction. reading a bit indicates the pin value 0x04 oen rw 0x00000000 gpio output enable register (1 bit per gpio) . 0: input mode. 1: output mode 0x08 pe rw 0x03ffffff pull enable (1 bit per io). 0: pull disabled. 1: pull enabled 0x0c ds rw 0x00000000 io driver strength (1 bit per io). 0: 2ma. 1: 4 ma 0x10 is rw 0x00000000 interrupt sense register (1 bit per io). 0 : edge detection. 1: level detection 0x14 ibe rw 0x00000000 interrupt edge register (1 bit per io). 0: single edge. 1: both edges 0x18 iev rw 0x00000000 interrupt event register (1 bit per io). 0: falling edge or low level. 1: rising edge or high level 0x1c ie rw 0x00000000 interrupt mask register (1 bit per io). 0: interrupt disabled. 1: interrupt enabled. 0x24 mis r 0x00000000 masked interrupt status register (1 bit per io) 0x28 ic w 0x00000000 interrupt clear register (1 bit per io). 0: no effect. 1 : clear interrupt 0x2c mode0 rw 0x00000000 select mode for io0 to dio7. 000b: gpio mode. 001b: serial1 mode. 100b: serial0 mode. 101b: microphone/adc mode. refer to the detailed description below.
functional details bluenrg - 1 112 / 173 docid028866 rev 1 address offset name rw reset description 0x30 mode1 rw 0x00000110 select mode for io8 to io14. 000 b: gpio mode. 001b: serial1 mode. 100b: serial0 mode. 101b: microphone/adc mode. refer to the detailed description below. 0x3c dats rw 0x00000000 set some bits of data when in gpio mode without affecting the others (1 bit per io). 0: no effect. 1: set at 1 the bit 0x40 datc rw 0x00000000 clear some bits of data when in gpio mode without affecting the others (1 bit per io). 0: no effect. 1: clear at 0 the bit 0x44 mftx rw 0x00000000 select the io to be used as capture input for the mftx timers. refer to t he detailed description below. table 132: gpio C data register description: address offset gpio_base_addr+0x00 bit field name reset rw description 31:0 data 0x00000000 rw io0 to io14 data value. writing to a bit will drive the written value on the corre sponding io when it is configured in gpio mode and the output direction. reading a bit indicates the pin value. table 133: gpio C oen register description: address offset gpio_base_addr+0x04 bit field name reset rw description 31:0 oen 0x00000000 rw gpi o output enable register (1 bit per gpio). ? 0: input mode. ? 1: output mode. table 134: gpio C pe register description: address offset gpio_base_addr+0x08 bit field name reset rw description 31:0 pe 0x03ffffff rw pull enable (1 bit per io). ? 0: pull disable d. ? 1: pull enabled. table 135: gpio C ds register description: address offset gpio_base_addr+0x0c bit field name reset rw description 31:0 ds 0x00000000 rw io driver strength (1 bit per io). ? 0: 2ma. ? 1: 4 ma.
bluenrg - 1 functional details docid028866 rev 1 113 / 173 table 136: gpio C is register description: address offset gpio_base_addr+0x10 bit field name reset rw description 31:0 is 0x00000000 rw interrupt sense register (1 bit per io). ? 0: edge detection ? 1: level detection table 137: gpio C ibe register description: address offset gpio_base_addr+0x14 b it field name reset rw description 31:0 ibe 0x00000000 rw interrupt edge register (1 bit per io). ? 0: single edge ? 1: both edges table 138: gpio C iev register description: address offset gpio_base_addr+0x18 bit field name reset rw description 31:0 iev 0x00000000 rw interrupt event register (1 bit per io). ? 0: falling edge or low level ? 1: rising edge or high level table 139: gpio C ie register description: address offset gpio_base_addr+0x1c bit field name reset rw description 31:0 ie 0x00000000 rw in terrupt mask register (1 bit per io). ? 0: interrupt disabled. ? 1: interrupt enabled. table 140: gpio C mis register description: address offset gpio_base_addr+0x24 bit field name reset rw description 31:0 mis 0x00000000 r masked interrupt status register (1 bit per io). table 141: gpio C ic register description: address offset gpio_base_addr+0x28 bit field name reset rw description 31:0 ic 0x00000000 w interrupt clear register (1 bit per io). ? 0: no effect ? 1: clear interrupt table 142: gpio - mode0 r egister description: address offset gpio_base_addr+0x2c bit field name reset rw description 2:0 io0 0x0 rw io0 mode 3 reserved 0x0 r reserved 6:4 io1 0x0 rw io1 mode 7 reserved 0x0 r reserved 10:8 io2 0x0 rw io2 mode
functional details bluenrg - 1 114 / 173 docid028866 rev 1 bit field name reset rw description 11 reserved 0x0 r reserved 14:12 io3 0x0 rw io3 mode 15 reserved 0x0 r reserved 18:16 io4 0x0 rw io4 mode 19 reserved 0x0 r reserved 22:20 io5 0x0 rw io5 mode 23 reserved 0x0 r reserved 26:24 io6 0x0 rw io6 mode 27 reserved 0x0 r reserved 30:28 dio7 0x0 rw dio7 mode 31 reserved 0x0 r reserved table 143: gpio C mode1 register description: address offset gpio_base_addr+0x30 bit field name reset rw description 2:0 io8 0x0 rw io8 mode 3 reserved 0x0 r reserved 6:4 io9 0x1 rw io9 mode 7 reserved 0x0 r reserved 10:8 io10 0x1 rw io10 mode 11 reserved 0x0 r reserved 14:12 io11 0x0 rw io11 mode 15 reserved 0x0 r reserved 18:16 io12 0x0 rw io12 mode 19 reserved 0x0 r reserved 22:20 io13 0x0 rw io13 mode 23 reserved 0x0 r reserved 26:24 io14 0x0 rw io14 mode 31:27 reserved 0x 0 r reserved table 144: gpio C dats register description: address offset gpio_base_addr+0x3c bit field name reset rw description 31:0 dats 0x00000000 rw set some bits of data when in gpio mode without affecting the others (1 bit per io). ? 0: no effect ? 1 : set at 1 the bit
bluenrg - 1 functional details docid028866 rev 1 115 / 173 table 145: gpio C datc register description: address offset gpio_base_addr+0x40 bit field name reset rw description 31:0 datc 0x00000000 rw clear some bits of data when in gpio mode without affecting the others (1 bit per io). ? 0: no effect ? 1: clear at 0 the bit table 146: gpio - mftx register description: address offset gpio_base_addr+0x44 bit field name reset rw description 7:0 mft1_timer_a 0x0 rw mft1 timer a. ? 0x00: io0. ? 0x01: io1 ? 0x02: io2 ? ... ? 0x0e: io14 15:8 mft1_timer_b 0x0 rw mft1 timer b. ? 0x00: io0. ? 0x01: io1 ? 0x02: io2 ? ... ? 0x0e: io14 23:16 mft2_timer_a 0x0 rw mft2 timer a. ? 0x00: io0. ? 0x01: io1 ? 0x02: io2 ? ... ? 0x0e: io14 31:24 mft2_timer_b 0x0 rw mft2 timer b. ? 0x00: io0. ? 0x01: io1 ? 0x02: io2 ? ... ? 0x0e: io14
functional details bluenrg - 1 116 / 173 docid028866 rev 1 3.13 mft 3.13.1 mft introduction the bluenrg - 1 integrates two multi functions timers (mft). main features are: ? two 16 - bit programmable timer/counters. ? two 16 - bit reload/capture registers that function either as reload registers or as capture registers, depending on the mode of operation. ? an 8 - bit fully programmable clock prescaler. ? clock source selectors that allow each counter to operate in: ? pulse - accumulate mode ? external - event mode ? prescaled system clock mode ? slow clock input mode ( available only if 32 mhz system clock is used, allows to divide by 2 and obtains a 16 mhz system clock as clock source). ? two i/o pins (tna and tnb) with programmable edge detection that operate as: ? capture and preset inputs ? external event (clock) inputs ? p wm outputs. ? two interrupts, one for each counter, that can be triggered by a: ? timer underflow ? timer reload ? input capture ? pulse train for generation of single or multiple pwm pulses. 3.13.2 mft functional description the mft can be configu red in five different modes. at each mode is associated a particular function for the two timers both for counter and reload registers as reported in table 147: "mft modes" . table 147: mft modes mode description timer count er 1 (tncnt1) reload / capture a (tncrb) reload / capture b (tncrb) timer counter 2 (tncnt2) 1 pwm and system timer or external event counter counter for pwm auto reload a = pwm time 1 auto reload b = pwm time 2 system time or external event 1a pwm pulse train counter for pwm auto reload a = pwm time 1 auto reload b= pwm time 2 pulse counter 2 dual - input capture and system timer capture a and b time base capture timer/counter 1 value upon tna event capture timer/counter 1 value upon tnb event system time r 3 dual independent timer time base for first timer reload register fortimer/counter 1 reload register for timer/counter 2 time base for second timer 4 single - input capture and single timer time base for first timer reload register fortimer/counter 1 ca pture timer/counter 1 value upon tnb event capture b time base
bluenrg - 1 functional details docid028866 rev 1 117 / 173 3.13.2.1 mft mode 1: processor - independent pwm in mode1, the timer counter 1 (tncnt1) can be used to generate a pwm signal on an output pin of the device. in this mode, the pwm output can emulate a clock signal with customized duty - cycle. indeed, the tncnt1 is alternatively reloaded by tncrb and tncrb registers. the initial value of the pwm output signal can be selected by software to be either high or low thanks to the tnaout b it in tnmctrl register. this bit impacts which reload value, is used for high level and low level of the pwm signal as shown in figure 11: "pwm signal" below. figure 11 : pwm signal when started t he first time, the tncnt1 starts with value preprogrammed in the register and count down at the clock rate selected by the timer/counter 1 clock selector (tnckc register). when an underflow occurs, the tncnt1 is reloaded alternatively with tncrb and tncrb registers (in this order) and counting proceeds downward from the loaded value. any time the counter is stopped by choosing "no - clock" by the timer/counter 1 clock selector, it will obtain its first reload value after it has been started again from the tnc rb register. each time the counter is stopped and then restarted, it obtains its first reload value from the tncrb register. this is true whether the timer is restarted upon reset, after entering mode 1 from another mode, or after stopping and restarting t he clock with the timer/counter1 clock selector. in figure below the block diagram related to the mft mode 1.
functional details bluenrg - 1 118 / 173 docid028866 rev 1 figure 12 : mft mode 1 block diagram in this mode, the timer toggles the tna output upon underflow which is connected to pwmx pin of the bluenrg1. this generates a clock signal on tna with the width and duty cycle controlled by the values stored in the tncrb and tncrb registers. this is a "processor - independent" pwm clock because once the timer is set up, no more interact ion is required from the software and the cpu in order to generate the pwm signal. the timer can generate separate interrupts upon reload from tncrb and tncrb. the tnapnd or tnbpnd flags, which are set by the hardware upon occurrence of a timer reload, ind icate which interrupt has occurred. in this mode of operation, timer/counter 2 can be used as a simple system timer or an external - event counter. counter tncnt2 counts down with the clock selected by the timer/counter 2 clock selector, and can be configure d to generate an interrupt upon underflow if enabled by the tndien bit. the interrupts can be enabled or disabled by software. 3.13.2.2 mft mode 1a: pwm pulse - train mode mode1a is used to output a pwm signal thanks to timer/counter 1 as for mode1 but only in a time window defined by the timer/counter2. indeed, the timer/counter2 is used to specify the number of pulses to output on the io. the mode1a corresponds to the mode1 selected in the tnmdsel field of tnmctrl register with in addition th e tnpten bit set in the tnmctrl register. in mode1a, the timer/counter 1 (tncnt1) will alternatively be reloaded by tncrb and tncrb registers after starting from tnct1 as for mode1 and toggle the tna output of the mft connected to pwmx io each time an unde rflow occurs. in parallel, a trigger pulse is sent to timer/counter 2 (tncnt2), decrementing it by one. if timer/counter 2 (tncnt2) has reached the underflow condition and the end - of - pulse
bluenrg - 1 functional details docid028866 rev 1 119 / 173 condition is detected by the trigger logic as well, the clock of ti mer/counter 1 (tncnt1) is disabled immediately. the figure below shows the block diagram related to the mft mode 1a. figure 13 : mft mode 1a block diagram in mode 1a, timer/counter 2 (tncnt2) behaves differently from the way it be haves in modes 1 to 4. if an underflow condition occurs, the counter is preset to 0x0000 and not 0xffff. the timer/counter 1 starts to count: ? either on an external event on tnb input, ? or by software if tnptse bit has been set by setting the tnptet bit. the start of count request through tnptet bit setting when software trigger option is chosen must be done after the mft is enabled (tnen bit in tnmctrl register). any time the counter is stopped by choosing "no - clock" by the timer/counter 1 clock selecto r (tnckc register), it will obtain its first reload value after it has been started again from the tncrb register. upon reset, the mft is disabled. every time this mode is entered, the first reload in this mode will be from register tncrb. once the underfl ow condition for tncnt2 has been reached, tncnt2 must be initialized again by the application. it is not reloaded by any reload register. timer/counter 2 can be configured to generate an interrupt upon underflow if enabled by the tndien bit. in pulse - train mode, the value of tncnt2 specifies the number of pulses to be generated, plus one additional pulse (tnctn2+1 number of pulses). in pulse - train mode, the trigger logic uses events on tnb to enable the timer/counter 1 clock. this function has to be enabled by setting the tnptste bit to 0.
functional details bluenrg - 1 120 / 173 docid028866 rev 1 tnb can be configured to sense either positive - going or negative - going transitions. timer/counter 1 can be configured to toggle the tna output bit upon underflow. this results in the generation of a pulse signal on tna, wi th the width and duty cycle controlled by the values stored in the tncrb and tncrb registers. this is a processor - independent pwm signal because once the timer is set up, no more interaction is required from the software or the cpu in order to generate one or more pwm signal pulses. the initial value of the pwm output signal can be selected by software to be either high or low. the timer can be configured to generate separate interrupts upon reload from tncrb and tncrb. the tnapnd or tnbpnd flags, which are set by the hardware upon occurrence of a timer reload, indicate which interrupt has occurred. the interrupts can be enabled or disabled under software control. 3.13.2.3 mft mode 2: dual - input capture mode the mode2 is used to capture transi tions on two selected input pads of the device. the timer/counter1 can be used to manage the dual - capture feature as follows: ? a transition on input pad connected to tna pin of the mft generates a transfer of tncnt1 register value in tncrb register. ? a tran sition on input pad connected to tnb pin of the mft generates a transfer of tncnt1 register value in tncrb register. the timer/counter2 can be used: ? as a system counter: to count down at the rate of the selected clock. note: the device input pad selection is done using mftx_iosel register. the transition edge to capture has to be defined in tnaedg and tnbedg bits of the tnmctrl register. the tna and tnb inputs can be configured to perform a counter preset to 0xffff upon reception of a valid capture event us ing tnaen and tnben bits in tnmctrl register. in this case, the current value of the counter is transferred to the corresponding capture register and then the counter is preset to 0xffff. using this approach directly allows the software to determine the on - time, off - time, or period of an external signal, while reducing cpu overhead. in figure 14: "mft mode 2 block diagram" below the block diagram related to the mft mode 2.
bluenrg - 1 functional details docid028866 rev 1 121 / 173 figure 14 : mft mode 2 block diagram the input signal on tna and tnb must have a pulse width equal to or greater than one system clock cycle. the values captured in the tncrb register at different times reflect the elapsed time between transitions on the tna pin. the same is true for the tncrb register and tnb pin. each input pin can be configured to sense either positive - going or negative - going transitions. the timer can be configured to generate interrupts on reception of a transition on either tna or tnb, which can be enabled or disabled separately by the tnaien and tnbien bits. an underflow of tncnt1 can generate an interrupt if enabled by the tncien bit. timer/counter 2 can be used as a simple system timer in this mode of operation. tncnt2 counts down with the clock selected b y the timer/counter 2 clock selector, and can be configured to generate an interrupt upon underflow if enabled by the tndien bit. tncnt1 cannot operate in the pulse - accumulate or extemal - event counter modes, since the tnb input is used as a capture input. selecting either of these modes for tncnt1 causes tncnt1 to be stopped. however, all available clock source modes may be selected for tncnt2. thus, it is possible to determine the number of capture events on tnb or the elapsed time between capture events on tnb by using tncnt2. 3.13.2.4 mft mode 3: dual independent timer/counter mode this mode3 allows using the two timer/counter 1 and 2 separately. the timer/counter1 can be used: ? as a system counter: to count down at the rate of the selecte d clock.
functional details bluenrg - 1 122 / 173 docid028866 rev 1 ? to generate a 50% duty - cycle clock signal on tna pin connected to the pwmx pin of the device (tncnt1 reloaded by tncrb on underflow). ? to be an event counter using tnb pin as an external event or pulse - accumulate input. the timer/counter2 can be us ed: ? as a system counter: to count down at the rate of the selected clock. ? to be an event counter using tnb pin as an external event or pulse - accumulate input. in figure below the block diagram related to the mft mode 3. figure 15 : mft mode 3 block diagram in mode 3, the timer/counter is configured to operate as a dual independent system timer or dual external - event counter. in addition, timer/counter 1 can generate a 50% duty cycle pwm signal on the tna pin. the tnb pin can be use d as an external - event input or pulse - accumulate input, and serve as the clock source to either timer/counter 1 or timer/counter 2. both counters can also be operated from the prescaled system clock. timer/counter 1 (tncnt1) counts down at the rate of the selected clock. upon underflow, tncnt1 is reloaded from the tncrb register and counting proceeds. if enabled, the tna pin toggles upon underflow of tncnt1. the initial value of the tna output can be selected by software to be either high or low. in additio n, the tnapnd interrupt - pending flag is set, and a timer interrupt 1 is generated if the tnaien bit is set. since tna toggles upon every underflow, a 50% duty - cycle pwm signal can be generated on tna without requiring any interaction of the software or the cpu. timer/counter 2 (tncnt2) counts down at the rate of the selected clock. upon every underflow of tncnt2, the value contained in the tncrb register is loaded into tncnt2 and counting proceeds downward from that value. in addition, the tndpnd interrupt - pending flag is set and a timer interrupt 2 is generated if the tndien bit is set.
bluenrg - 1 functional details docid028866 rev 1 123 / 173 3.13.2.5 mft mode 4: input - capture plus timer mode this mode4 is combination of mode3 and mode2. the timer/counter1 can be used: ? as a system counter: to cou nt down at the rate of the selected clock. ? to generate a 50% duty - cycle clock signal on tna pin connected to the pwmx pin of the device (tncnt1 reloaded by tncrb on underflow). the timer/counter2 can be used: ? as a system counter: to count down at the rate of the selected clock. ? a transition on input pad connected to tnb pin of the mft generates a transfer of tncnt2 register value in tncrb register. the device input pad selection is done using mftx_iosel register the transition edge to capture has to be defined in tnbedg bit of the tnmctrl register. the tnb input can be configured to perform a counter preset to 0xffff upon reception of a valid capture event using tnben bit in tnmctrl register. in figure below the block diagram related to the mft mode 4. figure 16 : mft mode 4 block diagram this mode is a combination of mode 3 and mode 2,and makes it possible to operate timer/counter 2 as a single input - capture timer while timer/counter 1 can be used as a system timer as described above. tncnt1 starts counting down once a clock has been enabled. upon underflow, tncnt1 is reloaded from the tncrb register, and counting proceeds downward from that value. if
functional detai ls bluenrg - 1 124 / 173 docid028866 rev 1 enabled, the tna pin toggles upon every underflow of tncnt1. the initial value of the tna output signal can be selected by software to be either high or low. in addition, the tnapnd interrupt - pending flag is set and a timer interrupt 1 is generated if the tnaien bit is set. since tna toggles upon every underflow, a 50% duty - cycle pw m signal can be generated on tna without requiring any interaction with the software or the cpu. tncnt2 starts counting down once a clock has been enabled. when a transition is received on tnb, the value contained in tncnt2 is transferred to tncrb, and the interrupt - pending flag tnbpnd is set. a timer interrupt 1is generated if enabled. the software can enable a preset of the counter to 0xffff upon detection of a transition on tnb. in this case, the current value of tncnt2 is transferred to tncrb, followed by a preset of the counter to 0xffff. tncnt2 starts counting downwards from 0xffff until the next transition is received on tnb, which causes the procedure of capture and preset to be repeated. the underflow of tncnt2 causes the tndpnd interrupt - pending fl ag to be set, and can also generate a timer interrupt 2 if enabled. the input signal on tnb must have a pulse width equal to or greater than one system clock cycle. tnb can be configured to sense either rising or falling edges. tncnt2 cannot operate in the pulse - accumulate or external - event counter modes since the tnb input is used as a capture input. selecting either of these modes for tncnt2 causes tncnt2 to be stopped. however, all available clock source modes may be selected for tncnt1. thus by using tn cnt1, it is possible to determine the number of capture events on tnb, or the elapsed time between capture events on tnb. 3.13.2.6 timer io functions there are two pins associated with each instance of the mftx. the pins are called tna and t nb. the functionality of tna and tnb depends on the mode of operation and the value of the tnaen and tnben bits. table 148: "mft io functions" shows the function of tna and tnb for various modes of operation. note that if t na functions as a pwm output, tnaout defines the initial and present value of tna. for example, if the user wishes to start with tna high, tnaout needs to be set before enabling the timer clock. table 148: mft io functions pin tnaen tnben mode 1 mode 1a mo de 2 mode 3 mode 4 pwm and counter pwm pulse train dual - input capture and counter dual independent counter input capture plus timer tna tnaen = 0 tnben = x no output no output capture tncnt1 into tncrb no output toggle no output toggle tnaen = 1 tnbe n = x toggle output on underflow of tncnt1 toggle output on underflow of tncnt1 capture tncnt1 into tncra and preset tncnt1 toggle output on underflow of tncnt1 tnb tnaen = x tnben = 0 external event or pulse accumulate input external event if tnptse = 0 capture tncnt1 into tncrb external event or pulse accumulate input capture tncnt2 into tncrb tnaen = x tnben = 1 external event or pulse accumulate input external event if tnptse = 0 capture tncnt1 into tncrb and preset tncnt1 external event or pulse ac cumulate input capture tncnt2 into tncrb and preset tncnt2
bluenrg - 1 functional details docid028866 rev 1 125 / 173 3.13.2.7 io configuration linked to mft timers the mft timers can be connected to the bluenrg1 io pins for the following features: ? input signal to trig the timer in capture mode. ? o utput signal when pwm mode is used (clock output emulation with controlled duty cycle) in capture mode, the timer waits for an external io event to start counting. the chosen io for capture is programmed through iosel_mftx register in io peripheral. this r egister allows configuring input capture io for timers a and b of both mft1 and mft2, depending on which timer(s) are configured in capture mode. in pwm mode, the signal is output on pwm0 io for mft1 and pwm1 for mft2. those ios are available at different location thanks to alternate option. so to output the chosen pwm signal, it is necessary to configure the io with the dedicated mode. 3.13.2.8 timers interrupts all sources have a pending flag associated with them, and can be enabled or disa bled by software. the pending flags are named tnxpnd, where n denotes the instance of the module, and x represents a letter from a to d. an interrupt enable flag (tnxien) is associated with each interrupt - pending flag. interrupt sources a, b and c can each generate a timer interrupt mft1a for mft1 and mft2a for mft2, whereas interrupt source d can generate a timer interrupt mft1b for mft1 and mft2b for mft2. not all interrupt sources are available in all modes. table 149: "mf t interrupt functions" shows which events can trigger an interrupt in which mode of operation. table 149: mft interrupt functions sys. int. interrupt pending flag mode 1 mode 1a mode 2 mode 3 mode 4 pwm and counter pwm pulse train dual - input capture an d counter dual independent counter input capture plus timer timer int. 1 (mft1a, mft2a) tnapnd tncnt1 reload from tncra tncnt1 reload from tncra input capture on tna transition tncnt1 reload from tncra tncnt1 reload from tncra tnbpnd tncnt1 reload from tncrb tncnt1 reload from tncrb input capture on tnb transition n/a input capture on tnb transition tncpnd n/a n/a tncnt1 underflow n/a n/a timer int. 2 (mft1b, mft2b) tndpnd tncnt2 underflow tncnt2 underflow tncnt2 underflow tncnt2 reload from tncrb tnc nt2 underflow
functional details bluenrg - 1 126 / 173 docid028866 rev 1 3.13.3 mft registers mft1 peripheral base address (mft1_base_addr) 0x40d00000. mft2 peripheral base address (mft2_base_addr) 0x40e00000. table 150: mftx registers address offset name rw reset description 0x00 tncnt1 rw 0 x00000000 timer / counter1 register 0x04 tncrb rw 0x00000000 capture / reload a register 0x08 tncrb rw 0x00000000 capture / reload b register 0x0c tncnt2 rw 0x00000000 timer / counter2 register 0x10 tnprsc rw 0x00000000 clock prescaler register 0x14 t nckc rw 0x00000000 clock unit control register. refer to the detailed description below. 0x18 tnmctrl rw 0x00000000 timer mode control register. refer to the detailed description below. 0x1c tnictrl rw 0x00000000 timer interrupt control register. refer t o the detailed description below. 0x20 tniclr w 0x00000000 timer interrupt clear register. refer to the detailed description below. table 151: mftx C tncnt1 register description: address offset mftx_base_addr+0x00 bit field name reset rw description 31 :0 tncnt1 0x00000000 rw register counter of timer1. table 152: mftx C tncra register description: address offset mftx_base_addr+0x04 bit field name reset rw description 31:0 tncra 0x00000000 rw register capture/reload a. table 153: mftx C tncrb regist er description: address offset mftx_base_addr+0x08 bit field name reset rw description 31:0 tncrb 0x00000000 rw register capture/reload b. table 154: mftx C tncnt2 register description: address offset mftx_base_addr+0x0c bit field name reset rw descript ion 31:0 tncnt2 0x00000000 rw register counter of timer2. table 155: mftx C tnprsc register description: address offset mftx_base_addr+0x10 bit field name reset rw description 31:0 tnprsc 0x00000000 rw clock prescaler register.
bluenrg - 1 functional details docid028866 rev 1 127 / 173 table 156: mftx - tnck c register description: address offset mftx_base_addr+0x14 bit field name reset rw description 2:00 tnc1csel 0x0 rw define the clock mode for timer/counter 1: ? 000b: no clock (timer/counter 1 stopped). ? 001b: prescaled system clock. 010b: external event o n tnb (mode 1 and 3 only). ? 011b: pulse accumulate (mode 1 and 3 only). 100b: low - speed clock. 5:3 tnc2csel 0x0 rw define the clock mode for timer/counter 2: ? 000b: no clock (timer/counter 1 stopped). ? 001b: prescaled system clock. 010b: external event on t nb (mode 1 and 3 only). ? 011b: pulse accumulate (mode 1 and 3 only). 100b: low - speed clock. 31:06 reserved 0x0 r reserved table 157: mftx - tnmctrl register description: address offset mftx_base_addr+0x18 bit field name reset rw description 1:00 tnmdsel 0x0 rw mftx mode select: ? 00b: mode 1 or 1a: pwm mode and system timer or pulse train ? 01b: mode 2: dual - input capture and system timer ? 10b: mode 3: dual independent timer/counter ? 11b: mode 4: single timer and single input capture 2 tnaedg 0x0 rw tna edge polarity:0: input is sensitive to falling edges.1: input is sensitive to rising edges. 3 tnbedg 0x0 rw tnb edge polarity:0: input is sensitive to falling edges.1: input is sensitive to rising edges. 4 tnaen 0x0 rw tna enable:0: tna in disable.1: tna in e nable. 5 tnben 0x0 rw tnb enable:0: tnb in disable.1: tnb in enable. 6 tnaout 0x0 rw tna output data:0: pin is low.1: pin is high. 7 tnen 0x0 rw mftx enable:0: mftx disable.1: mftx enable. 8 tnpten 0x0 rw tn pulse - train mode enable:0: mode 1a not selec ted.1: mode 1a selected (if tnmdsel = 00). 9 tnptse 0x0 rw tn pulse - train sofware trigger enable:0: no effect.1: pulse - train generation trigger (in mode 1a) 10 tnptet 0x0 rw tn pulse - train event trigger:0: no pulse - train event trigger occurred.1: pulse - t rain event trigger occurred (in mode 1a). 31:11:00 reserved 0x0 r reserved
functional details bluenrg - 1 128 / 173 docid028866 rev 1 table 158: mftx - tnictrl register description: address offset mftx_base_addr+0x1c bit field name reset rw description 0 tnapnd 0x0 r timer interrupt a pending: 0: no interru pt source pending. 1: interrupt source pending. 1 tnbpnd 0x0 r timer interrupt b pending: 0: no interrupt source pending. 1: interrupt source pending. 2 tncpnd 0x0 r timer interrupt c pending: 0: no interrupt source pending. 1: interrupt source p ending. 3 tndpnd 0x0 r timer interrupt d pending: 0: no interrupt source pending. 1: interrupt source pending. 4 tnaien 0x0 rw timer interrupt a enable: 0: interrupt disabled. 1: interrupt enabled. 5 tnbien 0x0 rw timer interrupt b enable: 0: int errupt disabled. 1: interrupt enabled. 6 tncien 0x0 rw timer interrupt c enable: 0: interrupt disabled. 1: interrupt enabled 7 tndien 0x0 rw timer interrupt d enable: 0: interrupt disabled. 1: interrupt enabled. 31:8 reserved 0x0 r reserved ta ble 159: mftx - tniclr register description: address offset mftx_base_addr+0x20 bit field name reset rw description 0 tnaclr 0x0 w 1: clear the timer pending flag a 1 tnbclr 0x0 w 1: clear the timer pending flag b. 2 tncclr 0x0 w 1: clear the timer pen ding flag c. 3 tndclr 0x0 w 1: clear the timer pending flag d. 31:4 reserved 0x0 r reserved 3.14 watchdog 3.14.1 introduction the watchdog timer provides a way of recovering from software crashes. the watchdog moni tors the interrupt and asserts a reset signal if the interrupt remains unserved for the entire programmed period. the watchdog clock is used to generate a regular interrupt, depending on a programmed value. it is counting down at a fixed frequency around 3 2.768 khz provided either by embedded rco or by the external xo 32 khz. main features are: ? 32 - bit down counter at fixed frequency 32.768 khz ? generate an interrupt each time the counter reaches zero ? generate an internal reset that reboot the system if the g enerated interrupt is not cleared by software and a second interrupt occurs
bluenrg - 1 functional details docid028866 rev 1 129 / 173 3.14.2 functional description the watchdog timer is a 32 - bit down counter that divides the clock input to produce an interrupt. the divide ratio is fully programma ble and controls the interrupt interval, which can be calculated as: interrupt interval = (wdt_load + 1) / (clock frequency in hz). the table below shows examples of wdt_load values. table 160: watchdog interrupt interval wdt_load interrupt interval (ms) 4294967295 131072000 65535 2000 32767 1000 4095 125 127 3.90625 63 1.953125 1 0.0610 a watchdog interrupt is generated each time the counter reaches zero. the counter is then reloaded with the content of the wdt_lr register. the interrupt status sh ould be cleared by writing to the interrupt clear register. when the interrupt is cleared, the counter is reloaded with the wdt_load value. if the interrupt status is not cleared and a new interrupt is generated, then a watchdog reset is generated, rebooti ng the system. the watchdog interrupt and reset generation can be enabled or disabled as required by the system using the relevant bits in the control register. when the interrupt generation is disabled the watchdog counter is also stopped, and when the in terrupt is enabled the counter will start from the programmed value, not the last - count value. write access to the registers within the watchdog timer can be disabled in the watchdog lock register. writing a value of 0x1acc_e551 to this wdt_lock register a llows write access to all other registers; writing any other value disables write access. this feature is included to allow some protection against software that might otherwise disable the watchdog functionality. 3.14.3 watchdog registers wdg peripheral base address (wdg_base_addr) 0x40700000. table 161: wdg registers address offset name rw reset description 0x00 lr rw 0xffffffff watchdog load register. refer to the detailed description below. 0x04 val r 0xffffffff watchdog value registe r. refer to the detailed description below. 0x08 cr rw 0x00000000 watchdog control register. refer to the detailed description below. 0x0c icr rw 0x00000000 watchdog interrupt clear register. refer to the detailed description below.
functional details bluenrg - 1 130 / 173 docid028866 rev 1 address offset name rw reset description 0x10 ris r 0x0000000 0 watchdog raw interrupt status register. refer to the detailed description below. 0x14 mis r 0x00000000 watchdog masked interrupt status register. refer to the detailed description below. 0xc00 lock rw 0x00000000 watchdog lock register. refer to the det ailed description below. table 162: wdg - lr register description: address offset wdg_base_addr+0x00 bit field name reset rw description 31:0 load 0xffffffff rw watchdog load value. value from which the counter is to decrement. when this register is wri tten to, the count is immediately restarted from the new value. table 163: wdg - val register description: address offset wdg_base_addr+0x04 bit field name reset rw description 31:0 wdtval 0xffffffff r watchdog load value. when read, returns the current value of the decrementing watchdog counter. a write has no effect. table 164: wdg - cr register description: address offset wdg_base_addr+0x08 bit field name reset rw description 0 inten 0x0 rw watchdog interrupt enable. enable the interrupt event: 0: watchdog interrupt is disabled. 1: watchdog interrupt is enabled. 1 resen 0x0 rw watchdog reset enable. enable the watchdog reset output: 0: watchdog reset is disabled. 1: watchdog reset is enabled. 31:2 reserved 0x0 r reserved table 165: wdg - icr reg ister description: address offset wdg_base_addr+0x0c bit field name reset rw description 31:0 wdticlr 0x0 rw watchdog interrupt enable: writing any value will clear the watchdog interrupt and reloads the counter from the lr register. a read returns zero.
bluenrg - 1 functional details docid028866 rev 1 131 / 173 table 166: wdg - ris register description: address offset wdg_base_addr+0x10 bit field name reset rw description 0 ris 0x0 r watchdog raw interrupt status bit. reflects the status of the interrupt status from the watchdog: 0: watchdog interrupt is not active. 1: watchdog interrupt is active. read - only bit. a write has no effect. 31:1 reserved 0x0 r reserved table 167: wdg - mis register description: address offset wdg_base_addr+0x14 bit field name reset rw description 0 mis 0x0 r watchdog masked in terrupt status bit. masked value of watchdog interrupt status: 0: watchdog interrupt is not active. 1: watchdog interrupt is active. read - only bit. a write has no effect. 31:1 reserved 0x0 r reserved table 168: wdg - lock register description: address o ffset wdg_base_addr+0xc00 bit field name reset rw description 31:0 lockval 0x0 rw watchdog lock value. when read, returns the lock status: 0: write access to all watchdog other registers is enabled. 1: write access to all watchdog other registers is disab led. when written, allows enabling or disabling write access to all other watchdog registers: writing 0x1acce551: write access to all other registers is enabled. writing any other value: write access to all other registers is disabled.
functional details bluenrg - 1 132 / 173 docid028866 rev 1 3.15 rtc 3.15.1 introduction the rtc timer can be used to provide an interrupt at regular time intervals. it generates an interrupt signal when it reaches zero after decrementing for a programmed number of cycles of the real - time clock input. the rtc timer can restart automatically from a load value when reaching zero if the auto restart mode is enabled, or it can stop when it reaches zero. the rtc is clocked by the 32 khz clock and is switched off in low - power modes which prevents this timer to be used for wakeup events. 3.15.2 functional description the rtc peripheral can be used either as real - time clock timer or as real - time clock watch. 3.15.2.1 real - time clock timer the real - time clock timer (rtc time r) can be used to provide an interrupt at regular time intervals. the rtc timer can restart automatically from a load value when reaching zero if the auto restart mode is enabled, or it can stop when it reaches zero. the rtc timer has the following feature s: ? 32 - bit down - counter. ? interrupt generation when timer reaches zero. ? start, auto restart (after counts to zero) and stop capability. ? on - the - fly register read and write access. ? 1/32 khz minimum period. ? multiple modes: periodic interrupt and single interrup t generation. ? capability to switch between two load values in periodic mode. the timer reloads alternatively from one load value to the other and the down - counter starts decrementing every 31.25 s (on average). the rtc timer is a 32 - bit free - running count er, clocked by the 32 khz clock signal (from an embedded 32 khz rc), that works in two modes: periodic and one - shot. table 169: rtc modes rttos bit mode description 0b periodic the counter generates an interrupt at a constant interval, reloading a load va lue after wrapping past zero. there are two load values: rtc_tlr1 for pattern value 0 and rtc_tlr2 for pattern value 1. 1b one - shot the counter generates an interrupt once. when the counter reaches zero, it halts until the user restarts it by: setting bit rtten in the rtc_tcr register of writing a new value to the load register rtc_tlr1 the rtc timer load registers define the values from which the counter restarts alternatively. in periodic mode, the timer must be stopped by the software before writing t o a load register. the counter loads a value from rtc_tlr1 or from rtc_tlr2, depending on the value of the current pattern value that crosses the pattern register to decide after each interrupt generation, which value to load. the number of pattern bits to be crossed
bluenrg - 1 functional details docid028866 rev 1 133 / 173 periodically (from the 128 bits) is specified in rtc_tcr [10:4]. this process offers the possibility to have better precision of the average tick period. in one - shot mode, the timer stops when it reaches zero, but the software can also stop it. once the counter is halted, the load registers (rtc_tlr1, rtc_tlr2) can be written and the counter considers the new written value. after a write, rtten (rtc_tcr) is set if the timer is in self - start mode. writing to rtc_tlr1 or rtc_tlr2 has no effect when the counter is running (the registers contents are not changed). 3.15.2.2 real - time clock watch the rtc clock watch consists of two counters and two alarm registers that have the following features: ? two counters: ? counts seconds, minut es, hours, days of the week, days of the month. ? counts years. ? two alarm registers: ? to trigger an interrupt at exact date and time. the clock watch counters are split in two registers: the rtc_cwdr register that holds: ? seconds on six bits. valid values are 0 to 59. (60, 61, 62 and 63 are invalid values, programming the rtc_cwdr with these values leads to unpredictable behavior.) the seconds are incremented on the clk1hz clock rate. ? minutes on six bits. valid values are 0 to 59 (60, 61, 62 and 63 are invalid values, programming the rtc_cwdr with these values leads to unpredictable behavior.) ? hours on five bits. valid values are 0 to 23 (24 to 31 are invalid values, programming the rtc_cwdr with these values leads to unpredictable behavior.) ? the day of the week on three bits. valid values are 1 (sunday) to 7 (saturday) (0 is an invalid value, programming the rtc_cwdr with this value leads to unpredictable behavior.) ? the day of the month on five bits. valid values are 1 to 31 for january, march, may, july, august , october and december, 1 to 30 for april, june, september, and november, 1 to 29 for february on leap years, or 1 to 28 for february on non - leap years. all other values are invalid values. programming the rtc_cwdr with these values leads to unpredictable behavior.) ? the month on four bits. valid values are 1 (january) to 12 (december). 0, 13, 14 and 15 are invalid values, programming the rtc_cwdr with these values leads to unpredictable behavior. the rtc_cwyr register holds: ? the year, from 0 to 4096 the clo ck watch time and date can be changed by writing new settings in the rtc_cwdlr and rtc_cwylr load registers. the new setting is transferred to the clock watch counters on the next clk1hz rising edge after the rtc_cwdlr register has been written. after each increment of the clock watch counters, the rtc_cwdr and rtc_cwyr registers are compared to the clock watch match registers, rtc_cwdmr and rtc_cwymr.
functional details bluenrg - 1 134 / 173 docid028866 rev 1 if both pairs of registers match, the internal interrupt signal rtcwintr is raised. to ignore the correspo nding bit - field of the rtc_cwdr register during the comparison, program the month (cwmonthm), day of the month (cwdaymm) or day of the week (cwdaywm) bit - fields of the rtc_cwdmr register with zero values. to ignore the rtc_cwyr register during the comparis on, program the year bit - fields of rtc_cwymr register with zero values. 3.15.2.3 rtc interrupts the rtc generates two internal interrupt signals: ? rtcintr: raised when the two clock watch counter registers (rtc_cwdr and rtc_cwyr) match the tw o clock watch alarm registers (rtc_cwdmr and rtc_cwymr). some bit - fields can be dont care during the comparison if a zero value is used for year, month, day of month and day of week. the software must clear this interrupt by writing 1 in the bit rtccwic of rtc_icr register. ? rttintr: raised when the full 32 - bit down - counter rtc_tdr reaches zero and is only cleared by writing 1 in the bit rttic of the rtc_icr register. the most significant carry bit of the counter detects the counter reaches zero. the soft ware must clear this interrupt by writing 1 in the bit rtctic of the rtc_icr register. each individual interrupt can be masked by writing 0b to its corresponding interrupt mask set/clear bit in the rtc_imsc register. both the raw interrupt status (prior to masking) and the final interrupt status (after masking) for each individual interrupt signal can be read from the rtc_ris and rtc_mis status registers. the rtc delivers also a single combined interrupt signal, rtuintr. this interrupt line is the logical o r of the both internal interrupt signals described above and is the signal connected to the processor interrupt line. 3.15.3 rtc registers rtc peripheral base address (rtc_base_addr) 0x40f00000. table 170: rtc registers address offset name rw reset description 0x00 cwdr r 0x02120000 clockwatch data register. refer to the detailed description below. 0x04 cwdmr rw 0x00000000 clockwatch data match register. refer to the detailed description below. 0x08 cwdlr rw 0x00000000 clockwatch data lo ad register. refer to the detailed description below. 0x0c cwyr r 0x00002000 clockwatch year register. refer to the detailed description below. 0x10 cwymr rw 0x00002000 clockwatch year match register. refer to the detailed description below. 0x14 cwylr rw 0x00000000 clockwatch year load register. refer to the detailed description below. 0x18 ctcr rw 0x00007fff control trim and counter register. refer to the detailed description below. 0x1c imsc rw 0x00000000 rtc interrupt mask register. refer to the de tailed description below.
bluenrg - 1 functional details docid028866 rev 1 135 / 173 address offset name rw reset description 0x20 ris r 0x00000000 rtc raw interrupt status register. refer to the detailed description below. 0x24 mis r 0x00000000 rtc masked interrupt status register. refer to the detailed description below. 0x28 icr w 0x00000000 rtc in terrupt clear register. refer to the detailed description below. 0x2c tdr r 0xffffffff rtc timer load value 0x30 tcr rw 0x00000000 rtc timer control register. refer to the detailed description below. 0x34 tlr1 rw 0x00000000 rtc timer first load register 0x38 tlr2 rw 0x00000000 rtc timer second load register 0x3c tpr1 rw 0x00000000 rtc timer pattern register (pattern[31:0]) 0x40 tpr2 rw 0x00000000 rtc timer pattern register (pattern[63:32]) 0x44 tpr3 rw 0x00000000 rtc timer pattern register (pattern[9 5:64]) 0x48 tpr4 rw 0x00000000 rtc timer pattern register (pattern[127:96]) 0x4c tin rw 0x00000000 rtc timer interrupt number register table 171: rtc - cwdr register description: address offset rtc_base_addr+0x00 bit field name reset rw description 5: 0 cwsec 0x0 r rtc clockwatch second value. clockwatch seconds: 0 to 59 (max 0x3b). 11:6 cwmin 0x0 r rtc clockwatch minute value. clockwatch seconds: 0 to 59 (max 0x3b). 16:12 cwhour 0x0 r rtc clockwatch hour value. clockwatch seconds: 0 to 23 (max 0x17). 19:17 cwdayw 0x1 r rtc clockwatch day of week value. clockwatch day of week: 001b: sunday. 010b: monday. 011b: tuesday. 100b: wednesday. 101b: thursday. 110b: friday. 111b: saturday. 24:20 cwdaym 0x1 r rtc clockwatch day of month value: 1 to 28/29/30 or 31. range of value to program depends on the month: 1 to 28: february month, non - leap year. 1 to 29: february month, leap year. 1 to 30: april, june, september, november month. 1 to 31: january, march, may, august, october, december month.
functional details bluenrg - 1 136 / 173 docid028866 rev 1 bit field name reset rw description 28:25 cwmonth 0x1 r rtc clockwatch month value: 0001b: january. ... 1100: december. 31:29 reserved 0x0 r reserved table 172: rtc - cwdmr register description: address offset rtc_base_addr+0x04 bit field name reset rw description 5:0 cwsecm 0x0 rw rtc clockwatch seco nd match value: 00 0000 to 11 1011: (0 to 59 or 0x00 to 0x3b) clockwatch seconds. 11 1100 to 11 1111 - (60 to 63 or 0x3c to 0x3f). non - valid data, match never occurs. 11:6 cwminm 0x0 rw rtc clockwatch minute match value: 00 0000 to 11 1011: (0 to 59 or 0x 00 to 0x3b) clockwatch minutes. 11 1100 to 11 1111 - (60 to 63 or 0x3c to 0x3f). non - valid data, match never occurs. 16:12 cwhourm 0x0 rw rtc clockwatch hour match value: 00000b to 10111b: (0 to 23 or 0x00 to 0x17) hour match value. 11000b to 11111b - (24 to 31 or 0x18 to 0x1f). non - valid data, match never occurs. 19:17 cwdaywm 0x0 rw rtc clockwatch day of week match value: 000b: day of week is don't care in the comparison. (default value after porn). 001b to 111b: (1 to 7) day of week match value. 24:20 cwdaymm 0x0 rw rtc clockwatch day of month match value: 0000b: (month is don't care in the comparison. default value after porn). 1 to 31: day of month match value. 28:25 cwmonthm 0x0 rw rtc clockwatch month match value: 0000b: (day of month is don't car e in the comparison. default value after porn). 0001b to 1100b: (1 to 12) month match value. 1101b (13, 0xd) to 1111b (0xf) non - valid data, match never occurs. 31:29 reserved 0x0 r reserved table 173: rtc - cwdlr register description: address offset rtc _base_addr+0x08 bit field name reset rw description 5:0 cwsecl 0x0 rw rtc clockwatch second load value. clockwatch seconds from 0 to 59 (0x3b). other values must not be used. 11:6 cwminl 0x0 rw rtc clockwatch minute load value. clockwatch minutes from 0 to 59 (0x3b). other values must not be used.
bluenrg - 1 func tional details docid028866 rev 1 137 / 173 bit field name reset rw description 16:12 cwhourl 0x0 rw rtc clockwatch hour load value. clockwatch hours from 0 to 23 (0x17). other values must not be used. 19:17 cwdaywl 0x0 rw rtc clockwatch day of week load value. clockwatch day of week: 000 b: must not be used. 001b: sunday. 010b: monday. 011b: tuesday. 100b: wednesday. 101b: thursday. 110b: friday. 111b: saturday. 24:20 cwdayml 0x0 rw rtc clockwatch day of month load value. 1 to 28/29/30 or 31 depending on month: 1 to 28: february month, no n - leap year. 1 to 29: february month, leap year. 1 to 30: april, june, september, november month. 1 to 31: january, march, may, august, october, december month. other values must not be used. 28:25 cwmonthl 0x0 rw rtc clockwatch month load value: 0001b: j anuary. ... 1100: december. other values must not be used. 31:29 reserved 0x0 r reserved table 174: rtc - cwyr register description: address offset rtc_base_addr+0x0c bit field name reset rw description 13:0 cwyear 0x2000 r rtc clockwatch year value. c lockwatch year, in bcd format is from 0 to 3999. 31:14 reserved 0x0 r reserved table 175: rtc - cwymr register description: address offset rtc_base_addr+0x10 bit field name reset rw description 13:0 cwyearm 0x2000 rw rtc clockwatch year match value. cl ockwatch year match value is in bcd format from 0 to 3999. 31:14 reserved 0x0 r reserved table 176: rtc - cwylr register description: address offset rtc_base_addr+0x14 bit field name reset rw description 13:0 cwyearl 0x0 rw rtc clockwatch year load val ue. clockwatch year load value is in bcd format from 0 to 3999. 31:14 reserved 0x0 r reserved
functional details bluenrg - 1 138 / 173 docid028866 rev 1 table 177: rtc - ctcr register description: address offset rtc_base_addr+0x18 bit field name reset rw description 14:0 ckdiv 0x7fff rw clock divider factor. t his value plus one represents the integer part of the clk32k clock divider used to produce the reference 1 hz clock. 0x000: clk1hz clock is similar to clk32k for rtc timer and stopped for rtc clockwatch. 0x0001: 2 clk32k clock cycles per clk1hz clock cycle . ... 0x7fff: 32768 clk32k clock cycles per clk1hz clock cycle (default value after porn reset). ... 0xffff: clk32k clock cycles per clk1hz clock cycle. writing to this bit - field will be disregarded if cwen = 1. a read returns the value of the ckdiv bit - fi eld. 15 reserved 0x0 r reserved 25:16 ckdel 0x0 rw trim delete count. this value represents the number of clk32k clock pulses to delete every 1023 clk32k clock cycles to get a better reference 1 hz clock for incrementing the rtc counter. 0x000: no clk32k clock cycle is deleted every 1023 clk1hz clock cycles (default value after porn reset). 0x001: 1 clk32k clock cycle is deleted every 1023 clk1hz clock cycles. ... 0x3ff: 1023 clk32k clock cycles are deleted every 1023 clk1hz clock cycles. writing to this bit - field will be disregarded if cwen = 1. a read returns the value of the ckdel bit - field. 26 cwen 0x0 rw clockwatch enable bit. when set to 1, the clockwatch is enabled. once it is enabled, any write to this register has no effect until a power - on reset . a read returns the value of the cwen bit value. 31:27 reserved 0x0 r reserved table 178: rtc - imsc register description: address offset rtc_base_addr+0x1c bit field name reset rw description 0 wimsc 0x0 rw rtc clock watch interrupt enable bit: when set to 0, clears the interrupt mask (default after porn reset). the interrupt is disabled. when set to 1, the interrupt for rtc clockwatch interrupt is enabled. 1 timsc 0x0 rw rtc timer interrupt enable bit: when set to 0, sets the mask for rtc timer inte rrupt (default after porn reset). the interrupt is disabled. when set to 1, clears this mask and enables the interrupt. 31:2 reserved 0x0 r reserved
bluenrg - 1 functional details docid028866 rev 1 139 / 173 table 179: rtc - ris register description: address offset rtc_base_addr+0x20 bit field name reset rw des cription 0 wris 0x0 r rtc clock watch raw interrupt status bit. gives the raw interrupt state (prior to masking) of the rtc clock watch interrupt. 1 tris 0x0 r rtc timer raw interrupt status bit. gives the raw interrupt state (prior to masking) of the rt c timer interrupt. 31:2 reserved 0x0 r reserved table 180: rtc - mis register description: address offset rtc_base_addr+0x24. bit field name reset rw description 0 wmis 0x0 r rtc clock watch interrupt status bit. gives the masked interrupt status (afte r masking) of the rtc clock watch interrupt wintr. 1 tmis 0x0 r rtc timer interrupt status bit. gives the masked interrupt status (after masking) of the rtc timer interrupt tintr. 31:2 reserved 0x0 r reserved table 181: rtc - icr register description: address offset rtc_base_addr+0x28 bit field name reset rw description 0 wic 0x0 w rtc clock watch interrupt clear register bit. clears the rtc clock watch interrupt wintr. 0: no effect. 1: clears the interrupt. 1 tic 0x0 w rtc timer interrupt clear regis ter bit. clears the rtc timer interrupt tintr. 0: no effect. 1: clears the interrupt. 31:2 reserved 0x0 r reserved table 182: rtc C tdr register description: address offset rtc_base_addr+0x2c bit field name reset rw description 31:0 tdr 0xffffffff r rt c time load value. table 183: rtc - tcr register description: address offset rtc_base_addr+0x30 bit field name reset rw description 0 os 0x0 rw rtc timer one shot count. 0: periodic mode (default). when reaching zero, the rtc timer raises its interrupt and is reloaded from the ld content. 1: one - shot mode. when reaching zero, the rtc timer raise its interrupt and stops.
functional details bluenrg - 1 140 / 173 docid028866 rev 1 bit field name reset rw description 1 en 0x0 rw rtc timer enable bit. 0: the rtc timer is stopped on the next clk32k cycle. 1: the rtc timer is enabled on the next clk32k cycle. when the rtc timer is stopped, the content of the counter is frozen. a read returns the value of the en bit. this bit set by hardware when the tlr register is written to while the counter is stopped. when the device is active, this bit is cleared by hardware when the counter reaches zero in one - shot mode. 2 s 0x0 rw rtc timer self start bit. when written to 1b, each write in a load register or a pattern will set en to 1b, so, start the counter in the next clk32k cycle. 3 reserved 0x0 r reserved 10 :4 sp 0x0 rw rtc timer pattern size. number of pattern bits crossed by the pointer. it defines the useful pattern size. 11 clk 0x0 rw rtc timer clock. 0: the rtc timer is clocked by clk32k. 1: the rtc timer is clocked by the trimmed clock. 12 bypass_gate d 0x0 rw enable or disable the internal clock gating: 0: the internal clock gating is activated. 1: no clock gating, clock is always enabled. 31:13 reserved 0x0 r reserved table 184: rtc C tlr1 register description: address offset rtc_base_addr+0x34 bit field name reset rw description 31:0 tlr1 0x00000000 rw rtc timer first load value. table 185: rtc C tlr2 register description: address offset rtc_base_addr+0x38 bit field name reset rw description 31:0 tlr2 0x00000000 rw rtc timer second load value. table 186: rtc C tpr1 register description: address offset rtc_base_addr+0x3c bit field name reset rw description 31:0 tpr1 0x00000000 rw rtc timer pattern register (pattern[31:0]). table 187: rtc C tpr2 register description: address offset rtc_base_a ddr+0x40 bit field name reset rw description 31:0 tpr2 0x00000000 rw rtc timer pattern register (pattern[63:32]). table 188: rtc C tpr3 register description: address offset rtc_base_addr+0x44 bit field name reset rw description 31:0 tpr3 0x00000000 rw rtc timer pattern register (pattern[95:64]).
bluenrg - 1 functional details docid028866 rev 1 141 / 173 table 189: rtc C tpr4 register description: address offset rtc_base_addr+0x48 bit field name reset rw description 31:0 tpr4 0x00000000 rw rtc timer pattern register (pattern[127:96]). table 190: rtc C tin r egister description: address offset rtc_base_addr+0x4c bit field name reset rw description 31:0 tin 0x00000000 rw rtc timer interrupt number register. 3.16 rng 3.16.1 introduction the rng is a real random number gene rator based on a continuous analog noise that provides a 16 - bit value to the host when read. 3.16.2 functional description the peripheral is normally used by the bluetooth stack, but the user can read the random value at an y time by accessing the register val. the rng peripheral is addressed through the ahb, so the access must be at 32 - bit, otherwise hard fault is generated on cortex m0. the minimum period between two consecutive random numbers is about 1.25 us. 3.16.3 rng register s rng peripheral base address (rng_base_addr) 0xb0000000 table 191: rng registers address offset name rw reset description 0x00 cr rw 0x00000000 rng configuration register. refer to the detailed description below. 0x04 sr r 0x 00000000 rng status register. refer to the detailed description below. 0x08 val r 0x00000000 rng 16 - bit random value. refer to the detailed description below. table 192: rng C cr register description: address offset rng_base_addr+0x00 bit field name res et rw description 1:0 reserved 0x0 rw reserved 2 dis 0x0 rw set the state of the random number generator. ? 0: rng is enable. ? 1: rng is disabled. the internal free - running oscillators are put in power - down mode and the rng clock is stopped at the input of the block. 31:3 reserved 0x00000000 rw reserved
functional details bluenrg - 1 142 / 173 docid028866 rev 1 table 193: rng C sr register description: address offset rng_base_addr+0x04 bit field name reset rw description 0 rdy 0x0 r new random value ready. ? 0: the val register value is not yet valid. if performin g a read access to val, the host will be put on hold until a random value is available. ? 1: the val register contains a valid random number. this bit remains at 0 when the rng is disabled (rngdis bit = 1b in cr) 31:1 reserved 0x00000000 r reserved table 194: rng C val register description: address offset rng_base_addr+0x08 bit field name reset rw description 15:0 random_value 0x0000 r the 16 - bit random value. 31:16 reserved 0x0000 r reserved 3.17 pdm stream processor the bluenrg - 1 integrates a digital filter for processing pdm stream coming from a digital microphone and inputting into a gpio pin. the bluenrg - 1 outputs a 0.8mhz or 1.6mhz signal into a gpio pin for providing the digital microphone with a frequency clock. 3.18 system timer (systick) the bluenrg - 1 includes a system timer (systick) that can be polled by software or can be configured to generate an interrupt. systick interrupt has its own entry in the vector table and therefore can have its own handler. 3.19 tx/rx event alert the bluenrg - 1 provided with dio14 pin a signal warning about a forthcoming transmission or receiving event. dio14 switches to high level about 100s before the bluenrg - 1 starts to transmit or receive and switches t o low level at the end of the transmission/receiving event. the signal can be used for controlling an external antenna switching and supporting coexistence with other wireless technology.
bluenrg - 1 functional details docid028866 rev 1 143 / 173 3.20 swd debug feature the bluenrg - 1 embeds the arm serial wire debug (swd) port. it is two pins (clock and single bi - directional data) debug interface, providing all the debug functionality plus real - time access to system memory without halting the processor or requiring any target resident code. tabl e 195: swd port pin functionality pin name pin description swclk dio9 swd clock signal swdio dio10 swd data signal 3.20.1 debugging tips there are certain situation where debug access is disabled and chip cannot be accessed. this includes the following cases: ? application that disable debug pins ? application that send the device in sleep or standby state, since in this state debug port is not powered. these cases are common during application development and device can end up in a state where debug access is no longer possible. to recover this situation, it is recommended to force io7 pin high and hardware reset the device in order to force execution of the updater code (see section 2.21 "pre - program med booloader" ). after this step users can connect with swd interface and erase the device flash memory. 3.21 bluetooth low energy radio the bluenrg - 1 integrates a rf transceiver compliant to the bluetooth specification and to the stand ard national regulations in the unlicensed 2.4 ghz ism band. the rf transceiver requires very few external discrete components. it provides 96 db link budgets with excellent link reliability, keeping the maximum peak current below 15 ma. in transmit mode, the power amplifier (pa) drives the signal generated by the frequency synthesizer out to the antenna terminal through a very simple external network. the power delivered as well as the harmonic content depends on the external impedance seen by the pa. 3.21.1 radi o operating modes several operating modes are defined for the bluenrg - 1 radio: ? reset mode ? sleep mode ? active mode ? radio mode ? rx mode ? tx mode in reset mode, the bluenrg - 1 is in ultra - low power consumption: all voltage regulators, cloc ks and the rf interface are not powered. the bluenrg - 1 enters reset mode by asserting the external reset signal. as soon as it is de - asserted, the device follows the normal activation sequence to transit to active mode.
functional details bluenrg - 1 144 / 173 docid028866 rev 1 in sleep mode either the low speed c rystal oscillator or the low speed ring oscillator are running, whereas the high speed oscillators are powered down as well as the rf interface. the state of the bluenrg - 1 is retained and the content of the ram is preserved. while in sleep mode, the bluenr g - 1 waits until an internal timer expires and then it goes into active mode. in active mode the bluenrg - 1 is fully operational: all interfaces, including rf, are active as well as all internal power supplies together with the high speed frequency oscillato r. the mcu core is also running. radio mode differs from active mode as also the rf transceiver is active and it is capable of either transmitting or receiving. 3.22 pre - programmed bootloader bluenrg - 1 device has a pre - programmed bootloa der supporting uart protocol with automatic baudrate detection. main features of the embedded bootloader are: ? auto baudrate detection up to 460 kbps ? flash mass erase, section erase ? flash programming ? flash readout protection enable/disable the pre - programm ed bootloader is an application which is stored on the bluenrg - 1 internal rom at manufacturing time by stmicroelectronics. this application allows upgrading the device flash with a user application using a serial communication channel (uart). bootloader i s activated by hardware by forcing dio7 high during power - up or hardware reset, otherwise, application residing in flash will be launched. the customer application must ensure that dio7 is forced low during power up. bootloader protocol is describ ed in a separate application note.
bluenrg - 1 pin description docid028866 rev 1 145 / 173 4 pin description the bluenrg - 1 is proposed in two package versions: wcsp34 offering 14 gpios and qfn32 offering 15 gpios. a dedicated automotive grade qfn32 package offers the same pin - out of the standard qfn32. figure 17: "bluenrg - 1 pin out top view (qfn32)" shows the qfn32 pin out and figure 18: "bluenrg - 1 ball out top view (wcsp34)" shows the wcsp34 ball out. figure 17 : bluenrg - 1 pin out top view (qfn32)
pin description bluenrg - 1 146 / 173 docid028866 rev 1 figure 18 : bluenrg - 1 ball out top view (wcsp34)
bluenrg - 1 pin description docid028866 rev 1 147 / 173 figure 19 : bluenrg - 1 ball out bottom view (wcsp34) table 196: pinout description pins name i/o descr iption 1 f1 dio10 i/o general purpose digital i/o 2 e1 dio9 i/o general purpose digital i/o 3 d3 dio8 i/o general purpose digital i/o 4 d2 dio7/boot a i/o bootloader pin/ general purpose digital i/o 5 d1 dio6 i/o general purpose digital i/o 6 a3 vbat 3 vdd battery voltage input 7 c2 dio5 i/o general purpose digital i/o 8 c3 dio4 i/o general purpose digital i/o 9 b1 dio3 i/o general purpose digital i/o 10 a1 dio2 i/o general purpose digital i/o 11 b2 dio1 i/o general purpose digital i/o 12 a2 dio0 i/o general purpose digital i/o 13 a5 anatest0/dio14 i/o analog output/ general purpose digital i/o a the pin dio7/boot is monitored by bootloader after power up or ha rdware reset and it should be low to prevent unwanted bootloader activation.
pin description bluenrg - 1 148 / 173 docid028866 rev 1 pins name i/o descr iption 14 d4 anatest1 o analog output 15 b4 adc1 i adc input 1 16 d5 adc2 i adc input 2 17 a6 fxtal1 i 16/32 mhz crystal 18 b5 fxtal0 i 16/32 mhz crystal 1 9 - vbat2 vdd battery voltage input 20 c6 rf1 i/o antenna + matching circuit connection 21 d6 rf0 i/o antenna + matching circuit connection 22 e4 sxtal1 i 32 khz crystal 23 e5 sxtal0 i 32 khz crystal 24 e6 vbat1 vdd battery voltage input 25 b3 resetn i system reset 26 f6 smpsfilt1 i smps output to external filter 27 f4 smpsfilt2 i/o smps output to external filter/battery voltage input 28 f3 vdd1v2 o 1.2 v digital core output 29 - dio13 i/o general purpose digital i/o 30 f2 dio12 i/o general purpo se digital i/o 31 e3 test i test pin put to gnd 32 e2 dio11 i/o general purpose digital i/o - a4 gnd gnd ground - b6 gnd gnd ground - c1 gnd gnd ground - f5 gnd gnd ground
bluenrg - 1 memory mapping docid028866 rev 1 149 / 173 5 memory mapping program memory, data memory, register s and i/o ports are organized within the same linear 4 - gbyte address space. the bytes are coded in memory in little endian format. the lowest numbered byte in a word is considered the words least significant byte and highest numbered byte the most signifi cant. the addressable memory space is divided into 16 main blocks, each 256 mb. all the memory areas that are not allocated to on - chip memories and peripherals are considered reserved. for the detailed mapping of an available memory and register areas, p lease refer to the memory map in table below and to the register lists detailed in each of the peripheral sections. table 197: memory mapping address cortex - m0 address map size description 0x0000_0000 C 0x0000_0fff code 4 kb rom 0x1000_0000 C 0x1000_0fff code 4 kb rom 0x1004_0000 C 0x1006_7fff code 160 kb flash 0x2000_0000 C 0x2000_2fff sram0 always on 12 kb sram 0x2000_3000 C 0x2000_5fff sram1 switchable 12 kb sram 0x2000_6000 C 0x3fff_ffff reserved 0x4000_0000 apb peripheral 4 kb gpio 0x4010_000 0 4 kb flash controller 0x4020_0000 4 kb system controller 0x4030_0000 4 kb uart 0x4040_0000 4 kb spi 0x4050_0000 4 kb reserved 0x4060_0000 4 kb reserved 0x4070_0000 4 kb watchdog 0x4080_0000 4 kb adc 0x4090_0000 4 kb clock generator 0x40 a0_0000 4 kb i2c2 0x40b0_0000 4 kb i2c1 a 0x40c0_0000 4 kb ahb up converter 0x40d0_0000 4 kb mft1 0x40e0_0000 4 kb mft2 0x40f0_0000 4 kb rtc 0x4010_0000 4 kb reserved a the i 2 c 1 is not available in wlcsp34 package.
memory mapping bluenrg - 1 150 / 173 docid028866 rev 1 address cortex - m0 address map size description 0x4800_0000 4 kb ble controller 0x4810_0000 4 kb ble clock generator 0x5 000_0000 ahb peripheral 4 kb reserved 0xa000_0000 4 kb dma controller 0xb000_0000 4 kb rng 0xc000_0000 4 kb pka 0xc000_0400 4 kb reserved 0xe000_0000 C 0xe00f_ffff private peripheral bus 1 mb cortex - m0 registers 0xe010_0000 C 0xefff_ffff reserved 256 mb reserved 0xf000_0000 C 0xffff_ffff 256 mb reserved all the peripherals are addressed by apb, except dma, rng and pka peripherals that are addressed by ahb. the peripherals dma, rng and pka that are addressed through the ahb, must be accessed on ly with 32 - bit accesses. any 8 - bit or 16 - bit access will generate an ahb error leading to a hard fault on cortex - m0.
bluenrg - 1 application circuit docid028866 rev 1 151 / 173 6 application circuit the schematics below are purely indicative. figure 20 : application cir cuit: active dc - dc converter qfn32 package figure 21 : application circuit: non - active dc - dc converter qfn32 package
application circuit bluenrg - 1 152 / 173 docid028866 rev 1 figure 22 : application circuit: active dc - dc converter wcsp34 package figure 23 : application circuit: non active dc - dc converter wcsp34 package
bluenrg - 1 application circuit docid028866 rev 1 153 / 173 table 198: external component list component description c1 decoupling capacitor c2 dc - dc converter output capacitor c3 decoupling capacitor for 1.2 v digital regu lator c4 decoupling capacitor for 1.2 v digital regulator c5 decoupling capacitor c6 32 khz crystal loading capacitor c7 32 khz crystal loading capacitor c8 rf balun/matching network capacitor c9 rf balun/matching network capacitor c10 rf balun/matc hing network capacitor c11 rf balun/matching network capacitor c12 rf balun/matching network capacitor c13 rf balun/matching network capacitor c14 rf balun/matching network capacitor c15 decoupling capacitor c16 16/32 mhz crystal loading capacitor c 17 16/32 mhz crystal loading capacitor c18 decoupling capacitor c19 dc - dc converter output capacitor l1 32 khz crystal filter inductor l2 16/32 mhz crystal filter inductor l3 rf balun/matching network inductor l4 rf balun/matching network inductor l 5 rf balun/matching network inductor xtal1 32 khz crystal (optional) xtal2 16/32 mhz crystal
absolute maximum ratings and thermal data bluenrg - 1 154 / 173 docid028866 rev 1 7 absolute maximum ratings and thermal data table 199: absolute maximum ratings pin parameter value unit 5, 19, 24, 26, 28 dc - dc convert er supply voltage input and output - 0.3 to +3.9 v 12, 29 dc voltage on linear voltage regulator - 0.3 to +3.9 v 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 25, 27, 30, 31, 32 dc voltage on digital input/output pins - 0.3 to +3.9 v 13, 14, 15,16 dc voltage on analog p ins - 0.3 to +3.9 v 17, 18, 22, 23 dc voltage on xtal pins - 0.3 to +1.4 v 20, 21 dc voltage on rf pins - 0.3 to +1.4 v tstg storage temperature range - 40 to +125 c vesd - hbm electrostatic discharge voltage 2.0 kv absolute maximum ratings are those values above which damage to the device may occur. functional operation under these conditions is not implied. all voltages are referred to gnd. table 200: thermal data symbol parameter value unit rthj - amb thermal resistance junction - ambient 34 (qfn32 ) 50 (wlcsp34) c/w rthj - c thermal resistance junction - case 2.5 (qfn32) 25 (wlcsp34) c/w
bluenrg - 1 general characteristics docid028866 rev 1 155 / 173 8 general characteristics table 201: recommended operating conditions symbol parameter min. typ. max. unit vbat operating battery supply vol tage 1.7 3.6 v t a operating ambient temperature range - 40 +105 c operating ambient temperature range for automotive grade level - 40 +105 c
electrical specification bluenrg - 1 156 / 173 docid028866 rev 1 9 electrical specification 9.1 electrical characteristics charact eristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat = 3.0 v. all performance data are referred to a 50 antenna connector, via reference design, qfn32 package version. table 20 2: electrical characteristics symbol parameter test conditions min. typ. max. unit power consumption when dc - dc converter active i bat supply current reset 5 na standby 500 na sleep mode: 32 khz xo on (24 kb retention ram) 0.9 a sleep mode : 32 khz ro on (24 kb retention ram) 2.1 active mode: cpu, flash and ram on 1.9 ma rx 7.7 ma tx +8 dbm 15.1 ma tx +4 dbm 10.9 tx +2 dbm 9 tx - 2 dbm 8.3 tx - 5 dbm 7.7 tx - 8 dbm 7.1 tx - 11 dbm 6.8 tx - 14 dbm 6.6 power consumption when dc - dc converter not active i bat supply current reset 5 na standby 500 na sleep mode: 32 khz xo on (24 kb retention ram) 0.9 a sleep mode: 32 khz ro on (24 kb retention ram) 2.1 ibat supply curre nt rx 14.5 ma tx +8 dbm 28.8 ma tx +4 dbm 20.5 tx +2 dbm 17.2 tx - 2 dbm 15.3 tx - 5 dbm 14 tx - 8 dbm 13
bluenrg - 1 electrical specification docid028866 rev 1 157 / 173 symbol parameter test conditions min. typ. max. unit tx - 11 dbm 12.3 tx - 14 dbm 12 9.1.1 peripheral current consumption table 203: perip heral current consumption peripheral typical consumption v dd = 3.0 v, t a = 25 c unit gpio 10 a flash controller 5 system controller 3 uart 80 spi 45 watchdog 4 adc 6 i2c1 95 i2c2 95 mft1 4 mft2 4 rtc 6 dma 14 note: the valu es are calculated as the increment to the current consumption when the peripheral is activated. the peripheral is activated if the related clock is provided. 9.2 rf general characteristics characteristics measured over recommended ope rating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v. all performance data are referred to a 50 antenna connector, via reference design, qfn32 package version. table 204: rf general characteristics symbol parameter test conditions min. typ. max. unit freq frequency range 2400 2483.5 mhz fch chan nel spacing 2 mhz rfch rf channel center frequency 2402 2480 mhz
electrical specification bluenrg - 1 158 / 173 docid028866 rev 1 9.3 rf transmitter characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat = 3.0 v. all performance data are referred to a 50 antenna connector, via reference design, qfn32 package version. table 205: rf transmitter characteristics symbol parameter test conditions min. typ. max. unit mod modulation scheme gfsk bt bandwidth - b it period product 0.5 mindex modulation index 0.5 dr air data rate 1 mbps pmax maximum output power at antenna connector +8 +10 dbm prfc minimum output power - 15 dbm pbw1m 6 db bandwidth for modulated carrier (1 mbps) using resolution bandwidth of 100khz 500 khz prf1 1 st adjacent channel transmit power 2 mhz using resolution bandwidth of 100 khz and average detector - 35 dbm prf2 2 nd adjacent channel transmit power >3mhz using resolution bandwidth of 100 khz and average detector - 40 dbm zload optimum differential load @ 2440 mhz 25.4 + j20.8 a ? 9.4 rf receiver characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c , v bat =3.0 v. all performance data are referred to a 50 antenna connector, via reference design, qfn32 package version. table 206: rf receiver characteristics symbol parameter test conditions min. typ. max. unit rxsens sensitivity ber <0.1% - 88 dbm psat saturation ber <0.1% 11 dbm zin input differential impedance @ 2440 mhz 25.5 - j14.2 rf selectivity with ble equal modulation on interfering signal c/ico - channel co - channel interference wanted signal = - 67 dbm, ber 0.1% 6 dbc c/i1 mhz ad jacent (+1 mhz) interference wanted signal = - 67 dbm, ber0.1% 0 dbc a simulated value
bluenrg - 1 electrical specification docid028866 rev 1 159 / 173 symbol parameter test conditions min. typ. max. unit c/i2 mhz adjacent (+2 mhz) interference wanted signal = - 67 dbm, ber 0.1% - 40 dbc c/i3 mhz adjacent (+3 mhz) interference wanted signal = - 67 dbm, ber 0.1% - 47 dbc c/i4 mhz adjacent ( 4 mhz) interference wanted signal = - 67 dbm, ber 0.1% - 46 dbc c/i6 mhz adjacent ( 6 mhz) interference wanted signal= - 67 dbm ber 0.1% - 48 dbc c/i25 mhz adjacent ( 25 mhz) interference wanted signal= - 67 dbm, ber 0.1% - 70 dbc c/iimage image frequency interference - 2 mhz wanted signal = - 67 dbm, ber 0.1% - 16 dbc c/iimage1 mhz adjacent (1 mhz) interference to in - band image frequency - 1 mhz - 3 mhz wanted signal = - 67 dbm, ber 0.1% 0 - 23 dbc intermodulation charact eristics (cw signal at f 1 , ble interfering signal at f 2 ) p_im(3) input power of im interferes at 3 and 6 mhz distance from wanted signal wanted signal = - 64dbm, ber 0.1% - 34 dbm p_im( - 3) input power of im interferes at - 3 and - 6 mhz distance from wan ted signal wanted signal = - 64 dbm, ber 0.1% - 48 dbm p_im(4) input power of im interferes at 4 and 8 mhz distance from wanted signal wanted signal = - 64 dbm, ber 0.1% - 34 dbm p_im(5) input power of im interferes at 5 and 10 mhz distan ce from wanted signal wanted signal = - 64 dbm, ber 0.1% - 34 dbm
electrical specification bluenrg - 1 160 / 173 docid028866 rev 1 9.5 high speed crystal oscillator characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are refer red to t a = 25 c, v bat = 3.0 v. table 207: high speed crystal oscillator characteristics symbol parameter test conditions min. typ. max. unit fnom nominal frequency 16/32 mhz ftol frequency tolerance includes initial accuracy, stability over temperat ure, aging and frequency pulling due to incorrect load capacitance. 50 ppm esr equivalent series resistance 100 ? pd drive level 100 w
bluenrg - 1 elec trical specification docid028866 rev 1 161 / 173 9.5.1 high speed crystal oscillator the bluenrg includes a fully integrated low power 16/32 mhz xtal oscillator with an embedded amplitude regulation loop. in order to achieve low power operation and good f requency stability of the xtal oscillator, certain considerations with respect to the quartz load capacitance c0 need to be taken into account. figure 24: "high speed oscillator block diagram" shows a simplified block diagr am of the amplitude regulated oscillator used on the bluenrg - 1. figure 24 : high speed oscillator block diagram low power consumption and fast startup time is achieved by choosing a quartz crystal with a low load capacitance c0. a reasonable choice for capacitor c0 is 12 pf. to achieve good frequency stability, the following equation needs to be satisfied: where c 1 =c 1 +c pcb1 +c pad , c 2 = c 2 +c pcb2 +c pad, where c 1 and c 2 are external (smd) components, c pcb1 and c pcb2 are pcb routing parasites and c pad is the equivalent small - signal pad - capacitance. the value of c pad is around 0.5 pf for each pad. the routing parasites should be minimized by placing quartz and c 1 /c 2 capacitors close to the chip, not only for an easier matching of the l oad capacitance c 0 , but also to ensure robustness against noise injection. connect each capacitor of the xtal oscillator to ground by a separate vias. *
electrical specification bluenrg - 1 162 / 173 docid028866 rev 1 9.6 low speed crystal oscillator characteristics characteristics measured over recomm ended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v. table 208: low speed crystal oscillator characteristics symbol parameter test conditions min. typ. max. unit fnom nominal frequency 32.768 khz ftol frequency tolerance includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance. 50 ppm esr equivalent series resistance 90 k? pd drive level 0.1 w these values are the correc t ones for nx3215sa - 32.768 khz - exs00a - mu00003. 9.7 high speed ring oscillator characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3 .0 v, qfn32 package version. table 209: high speed ring oscillator characteristics symbol parameter test conditions min. typ. max. unit f nom nominal frequency wlcsp34 14 mhz qfn32 13.6 9.8 low speed ring oscillator characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, qfn32 package version. table 210: low speed ring oscillator characteristics symbol parameter test condit ions min. typ. max. unit 32 khz ring oscillator (lsrosc) f nom nominal frequency 37.4 khz f tol frequency tolerance 500 ppm 9.9 n - fractional frequency synthesizer characteristics characteristics measured over recommended opera ting conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, f c = 2440 mhz.
bluenrg - 1 electrical specification docid028866 rev 1 163 / 173 table 211: n - fractional frequency synthesizer characteristics symbol parameter test conditions min. typ. max. unit pnsynth rf carrier phase n oise at 1 mhz offset from carrier - 113 dbc/hz at 3 mhz offset from carrier - 119 dbc/hz locktime pll lock time 40 s totime pll turn on / hop time including calibration 150 s 9.10 auxiliary blocks characteristics charac teristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, f c = 2440 mhz. qfn32 package version. table 212: auxiliary blocks characteristics symbol parameter test conditions m in. typ. max. unit analog - to - digital converter (adc) v dda analog supply voltage 1.7 3.0 3.6 v i dda, avg analog supply current average current during conversion 0.460 ma i dda, off analog supply current block disabled tbd na v inp, inn input pin vol tage with input attenuator - 50 mv (v bat +50 mv) / input attenuation v f clk clock frequency 1 mhz enob effective number of bits differential ended. decimation factor = 200, vbias = 0.6 v 10 12 bits single ended. decimation factor = 200, vbias = 0. 6 v 9 9.5 snr signal - to - noise ratio differential ended. decimation factor = 200, vbias = 0.6 v 75 db single ended. decimation factor = 200, vbias = 0.6 v 74 analog temperature sensor trange temperature range - 40 +105 c terr error in tempe rature (after calibration) - 4 0 +4 c tslope temperature coefficient 3.1 mv/c ticc current consumption 10 a
electrical specification bluenrg - 1 164 / 173 docid028866 rev 1 symbol parameter test conditions m in. typ. max. unit tts - out output voltage level 1 v battery indicator and brown - out reset (bor) a vblt1 battery level thresholds 1 2.7 v vblt2 batt ery level thresholds 2 2.5 v vblt3 battery level thresholds 3 2.3 v vblt4 battery level thresholds 4 2.1 v ablt battery level thresholds accuracy 5 % vabor ascending brown - out threshold 1.79 v vdbor descending brown - out threshold 1.73 v a bor must be disabled to allow the bluenrg - 1 to operate in the 1.7 - 2.0 v supply voltage range
bluenrg - 1 package information docid028866 rev 1 165 / 173 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definiti ons and product status are available at: www.st.com . ecopack ? is an st trademark.
package information bluenrg - 1 166 / 173 docid028866 rev 1 10.1 qfn32 package information figure 25 : qfn32 (5 x 5 x 1 pitch 0.5 mm) package outline qfn32_poa_8362854_b
bluenrg - 1 package information docid028866 rev 1 167 / 173 table 213: qfn32 (5 x 5 x 1 pitch 0.5 mm) mechanical data dim. mm min. typ. max. a 0.80 0.85 1.00 a1 0 0.02 0.05 a3 0.20 ref b 0.25 0.25 0.30 d 5.00 bsc e 5.00 bsc d2 3.2 3.70 e2 3.2 3.70 e 0.5 bsc l 0.30 0.40 0.50 0 14 k 0.20 figure 26 : qfn32 (5 x 5 x 1 pitch 0.5 mm) package detail "a"
package information bluenrg - 1 168 / 173 docid028866 rev 1 10.2 wlcsp34 package information figure 27 : wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline 1. the corner of terminal a1 must be ide ntified on the top surface by using a laser marking dot. wlcsp34_poa_8165249 see note 1
bluenrg - 1 package information docid028866 rev 1 169 / 173 table 214: wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data dim. mm. notes min. typ. max. a 0.50 a1 0.20 b 0.27 (1) d 2.50 2.56 2.58 (2) d1 2.00 e 2.60 2.66 2.68 (3) e1 2.00 e 0.40 f 0.28 g 0.33 ccc 0.05 notes: (1) the typical ball diameter before mounting is 0.25 mm. (2) d = f + d1 + f. (3) e = g + e1 + g.
pcb assembly guidelines bluenrg - 1 170 / 173 docid028866 rev 1 11 pcb assembly guidelines for flip chip mounting on the pcb, stmicroelectronics recommends the use of a solder stencil aperture of 330 x 330 m maximum and a typical stencil thickness of 125 m. flip chips are fully compatible with the use of near eutectic 95.8% sn, 3.5% ag, 0.7% cu solder paste with no - clean flux. st's recommendations for flip - chip board mounting are illustrated on the soldering reflow profile shown in figure 28: "flip chip csp (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation" . figure 28 : flip chip csp (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation table 215: flip chip csp (2 .71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation profile value typ. max. temp. gradient in preheat (t = 70 - 180 c/s 0.9 c/s 3 c/s temp. gradient (t = 200 - 225 c) 2 c/s 3 c/s peak temp. in reflow 240 - 245 c 260 c time ab ove 200 c 60 s 90 s temp. gradient in cooling - 2 to - 3 c - 6 c/s time from 50 to 220 c 160 to 220 c dwell time in the soldering zone (with temperature higher than 220 c) has to be kept as short as possible to prevent component and substrate damag e. peak temperature must not exceed 260 c. controlled atmosphere (n2 or n2h2) is recommended during the whole reflow, especially above 150 c. flip chips are able to withstand three times the previous recommended reflow profile to be compatible with a dou ble reflow when smds are mounted on both sides of the pcb plus one additional repair. a maximum of three soldering reflows are allowed for these lead - free packages (with repair step included).
bluenrg - 1 pcb assembly guidelines docid028866 rev 1 171 / 173 the use of a no - clean paste is highly recommended to avoid any cleaning operation. to prevent any bump cracks, ultrasonic cleaning methods are not recommended.
revision history bluenrg - 1 172 / 173 docid028866 rev 1 12 revision history date version changes 2 3 - jun - 2016 1 initial release.
bluenrg - 1 docid028866 rev 1 173 / 173 important noti ce C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers shoul d obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions diff erent from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document su persedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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